A set of Wishbone Controlled SPI Flash Controllers
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This repository has been repurposed from the original QSPI flash core repository. Instead of two large and monolithic QSPI flash cores for two different types of flash, this repository now contains three cores: a SPI flash core, a Dual SPI flash core, and a Quad SPI flash core which should be usable across a wider range of SPI flash chips. Even better, these new controllers use the DDR primitive for the SCK line, so they should be able to run twice as fast as the older cores.

The normal SPI flash core has been blogged about on ZipCPU.com.

  • Each of these cores has been formally verified, though not all of them have seen hardware (yet). SymbiYosys scripts for verification may be found in the bench/formal directory, together with GTKwave save files for viewing any resulting traces.

    If you'd like to get a glimpse of how these various cores might work, feel free to run SymbiYosys to generate demonstration cover traces.

  • A flash simulator has been placed into the bench/cpp directory. You may find this useful when simulating any of these flash cores using Verilator.

  • A software flash driver can be found in the sw directory. You may find this useful for writing values to any of these flash controllers. This driver has seen some simulation testing, but it has not (yet) been completed.

  • AutoFPGA scripts have been created for each flash device, though not yet tested.


Although this project has been around for quite some time, it is currently in the process of getting a massive rewrite. As of today, the RTL code is complete although it still needs to see hardware. The simulation software is also full featured, and has been used to simulate many flash devices. Work remains integrating the flash controllers into their various designs using AutoFPGA, as well as testing the various flash controllers in hardware once integrated. The software driver code will be used for this test, and will need to be full featured by then for that purpose.

In some, the following are left to do:

  • Write a simulation script to demonstrate each of the respective flash controllers. This would replace the old script from before the rewrite.

  • Update the AutoFPGA scripts to make certain they work with both Xilinx and iCE40 parts. (Intel parts remain in the distance)

    Currently, the QSPI flash controller works nicely in simultion within a different project.

  • Update the software flash driver so that one driver can apply to any controller

  • The last remains of the older driver, and its cousin need to be removed from the repository.

  • The specification needs some formatting work and editing.


These three cores, together with their supporting infrastructure, have been released under the LGPL license. You are welcome to use these cores under that license.