A Wishbone Controlled Scope for FPGA's
This is a generic/library routine for providing a bus accessed 'scope' or
(perhaps more appropriately) a bus accessed logic analyzer for use internal to
an FPGA. The general operation is such that this 'scope' can record and report
on any 32 bit value transiting through the FPGA that you have connected to the
scope. Once started and reset, the
scope records a copy of the input data every time the clock ticks with the
circuit enabled. That is, it records these values up until the trigger. Once
the trigger goes high, the scope will record for
bw_holdoff more counts
before stopping. Values may then be read from the buffer, oldest to most
recent. After reading, the scope may then be reset for another run.
In general, therefore, operation happens in this fashion:
- A reset is issued.
- Recording starts, in a circular buffer, and continues until
- The trigger line is asserted.
The scope registers the asserted trigger by setting the
- A counter then ticks until the last value is written.
The scope registers that it has stopped recording by setting the
- The scope recording is then paused until the next reset.
- While stopped, the CPU can read the data from the scope
- oldest to most recent
- one value per bus clock
- Writes to the data register reset the address to the beginning of the buffer
The Wishbone scope was featured on zipcpu.com as a conclusion to the discussion of the example debugging bus. That example discussed how to hook up the scope to your logic, as well as how to employ the scope software to create a VCD file that could then be viewed in GTKWave. The scope was also mentioned as a means of capturing traces of button bounces, with the short discussion of how to set it up for that task here.
Should you find the GPLv3 license insufficient for your needs, other licenses can be purchased from Gisselquist Technology, LLC.