Permalink
Switch branches/tags
Nothing to show
Find file Copy path
Fetching contributors…
Cannot retrieve contributors at this time
149 lines (132 sloc) 3.7 KB
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ./testb.h
//
// Project: ZBasic, a generic toplevel implementation using the full ZipCPU
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ../../../autofpga/trunk/sw/autofpga ../../../autofpga/trunk/sw/autofpga -o . global.txt bkram.txt buserr.txt clock.txt dlyarbiter.txt flash.txt rtclight.txt rtcdate.txt pic.txt pwrcount.txt version.txt busconsole.txt zipmaster.txt sdspi.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef TESTB_H
#define TESTB_H
#include <stdio.h>
#include <stdint.h>
#include <verilated_vcd_c.h>
#include "tbclock.h"
template <class VA> class TESTB {
public:
VA *m_core;
bool m_changed;
VerilatedVcdC* m_trace;
bool m_done;
unsigned long m_time_ps;
TBCLOCK m_clk;
TESTB(void) {
m_core = new VA;
m_time_ps = 0ul;
m_trace = NULL;
m_done = false;
Verilated::traceEverOn(true);
m_clk.init(10000); // 100.00 MHz
}
virtual ~TESTB(void) {
if (m_trace) m_trace->close();
delete m_core;
m_core = NULL;
}
virtual void opentrace(const char *vcdname) {
if (!m_trace) {
m_trace = new VerilatedVcdC;
m_core->trace(m_trace, 99);
m_trace->open(vcdname);
}
}
void trace(const char *vcdname) {
opentrace(vcdname);
}
virtual void closetrace(void) {
if (m_trace) {
m_trace->close();
delete m_trace;
m_trace = NULL;
}
}
virtual void eval(void) {
m_core->eval();
}
virtual void tick(void) {
m_time_ps+= 10000;
// Make sure we have all of our evaluations complete before the top
// of the clock. This is necessary since some of the
// connection modules may have made changes, for which some
// logic depends. This forces that logic to be recalculated
// before the top of the clock.
m_changed = true;
sim_clk_tick();
if (m_changed) {
eval();
if (m_trace) m_trace->dump(m_time_ps - 2500);
}
m_core->i_clk = 1;
eval();
if (m_trace) m_trace->dump(m_time_ps);
m_core->i_clk = 0;
eval();
if (m_trace) {
m_trace->dump(m_time_ps + 5000);
m_trace->flush();
}
}
virtual void sim_clk_tick(void) {
// Your test fixture should over-ride this
// method. If you change any of the inputs,
// either ignore m_changed or set it to true.
m_changed = false;
}
virtual bool done(void) {
if (m_done)
return true;
if (Verilated::gotFinish())
m_done = true;
return m_done;
}
virtual void reset(void) {
m_core->i_reset = 1;
tick();
m_core->i_reset = 0;
// printf("RESET\n");
}
};
#endif // TESTB