From fc861a5d42be374b26f749af37f976bb70eac304 Mon Sep 17 00:00:00 2001 From: ZipCPU Date: Mon, 19 Dec 2022 22:06:53 -0500 Subject: [PATCH] Fixed build on (newer) Verilators --- rtl/core/zipcpu.v | 10 +++++++--- sim/verilator/Makefile | 19 ++++++++++--------- sim/verilator/zipcpu_tb.cpp | 14 +++++++------- 3 files changed, 24 insertions(+), 19 deletions(-) diff --git a/rtl/core/zipcpu.v b/rtl/core/zipcpu.v index 69cf56f..8d2cf1d 100644 --- a/rtl/core/zipcpu.v +++ b/rtl/core/zipcpu.v @@ -310,6 +310,7 @@ module zipcpu(i_clk, i_reset, i_interrupt, wire op_stall, dcd_ce, dcd_phase; wire [3:0] dcd_opn; wire [4:0] dcd_A, dcd_B, dcd_R, dcd_preA, dcd_preB; + wire [6:0] full_dcd_R, full_dcd_A, full_dcd_B; wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; wire [3:0] dcd_F; wire dcd_wR, dcd_rA, dcd_rB, @@ -783,9 +784,9 @@ module zipcpu(i_clk, i_reset, i_interrupt, pf_instruction_pc, pf_valid, pf_illegal, dcd_valid, dcd_phase, dcd_illegal, dcd_pc, - { dcd_Rcc, dcd_Rpc, dcd_R }, - { dcd_Acc, dcd_Apc, dcd_A }, - { dcd_Bcc, dcd_Bpc, dcd_B }, + full_dcd_R, // { dcd_Rcc, dcd_Rpc, dcd_R }, + full_dcd_A, // { dcd_Acc, dcd_Apc, dcd_A }, + full_dcd_B, // { dcd_Bcc, dcd_Bpc, dcd_B }, dcd_preA, dcd_preB, dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn, dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock, @@ -799,6 +800,9 @@ module zipcpu(i_clk, i_reset, i_interrupt, `endif ); assign dcd_gie = pf_gie; + assign { dcd_Rcc, dcd_Rpc, dcd_R } = full_dcd_R; + assign { dcd_Acc, dcd_Apc, dcd_A } = full_dcd_A; + assign { dcd_Bcc, dcd_Bpc, dcd_B } = full_dcd_B; //}}} // diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 57e65ad..b64e5b7 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -128,7 +128,8 @@ CXX := g++ # in the rtl directory # CFLAGS := -Wall -Og -g -D__WORDSIZE=64 -DVM_COVERAGE=1 # -CFLAGS := -Wall -Og -g -D__WORDSIZE=64 +.DELETE_ON_ERROR: +CFLAGS := -Wall -faligned-new -Og -g -D__WORDSIZE=64 OBJDIR := obj-pc ZASM := ../../sw/zasm RTLD := ../../rtl @@ -152,7 +153,7 @@ SIMSRCS := memsim.cpp $(ZLIBSRCS) $(ZDMSRCS) SIMOBJS := $(addprefix $(OBJDIR)/,$(subst .cpp,.o,$(SIMSRCS) $(ZDSMSRCS))) SYSOBJS := $(OBJDIR)/zipsys_tb.o $(SIMOBJS) BONOBJS := $(OBJDIR)/zipbones_tb.o $(SIMOBJS) -VLSRCS := verilated.cpp verilated_vcd_c.cpp +VLSRCS := verilated.cpp verilated_vcd_c.cpp verilated_threads.cpp # # Use the verilated_cov.cpp source when you want to run Verilator coverage # (The CPU is covered better by the formal proofs ...) @@ -187,27 +188,27 @@ $(OBJDIR)/%.o: $(VROOT)/include/%.cpp $(CXX) $(CFLAGS) $(INCS) -c $< -o $@ zipsys_tb: $(SYSOBJS) $(VLOBJS) $(RAWSYSLIB) - $(CXX) $(CFLAGS) $(INCS) $(SYSOBJS) $(VLOBJS) $(SYSLIBS) -o $@ + $(CXX) $(CFLAGS) $(INCS) $(SYSOBJS) $(VLOBJS) $(SYSLIBS) -lpthread -o $@ zipbones_tb: $(BONOBJS) $(VLOBJS) $(RAWBONLIB) - $(CXX) $(CFLAGS) $(INCS) $(BONOBJS) $(VLOBJS) $(BONLIBS) -o $@ + $(CXX) $(CFLAGS) $(INCS) $(BONOBJS) $(VLOBJS) $(BONLIBS) -lpthread -o $@ div_tb: $(OBJDIR)/div_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vdiv__ALL.a testb.h - $(CXX) $(CFLAGS) $(VDEFS) $(INCS) $(OBJDIR)/div_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vdiv__ALL.a -o $@ + $(CXX) $(CFLAGS) $(VDEFS) $(INCS) $(OBJDIR)/div_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vdiv__ALL.a -lpthread -o $@ mpy_tb: $(OBJDIR)/mpy_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vcpuops__ALL.a testb.h - $(CXX) $(CFLAGS) $(VDEFS) $(INCS) $(OBJDIR)/mpy_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vcpuops__ALL.a -o $@ + $(CXX) $(CFLAGS) $(VDEFS) $(INCS) $(OBJDIR)/mpy_tb.o $(OBJDIR)/twoc.o $(VLIB) $(RTLOBJD)/Vcpuops__ALL.a -lpthread -o $@ zipmmu_tb: $(OBJDIR)/zipmmu_tb.o $(VLIB) $(BENCHOBJD)/Vzipmmu_tb__ALL.a - $(CXX) $(CFLAGS) $(VDEFS) $(INCS) -I$(BENCHOBJD) $(OBJDIR)/zipmmu_tb.o $(VLIB) $(BENCHOBJD)/Vzipmmu_tb__ALL.a -o $@ + $(CXX) $(CFLAGS) $(VDEFS) $(INCS) -I$(BENCHOBJD) $(OBJDIR)/zipmmu_tb.o $(VLIB) $(BENCHOBJD)/Vzipmmu_tb__ALL.a -lpthread -o $@ pfcache_tb: $(OBJDIR)/pfcache_tb.o $(OBJDIR)/memsim.o $(OBJDIR)/byteswap.o pfcache_tb: $(VLIB) $(RTLOBJD)/Vpfcache__ALL.a - $(CXX) $(CFLAGS) $(VDEFS) $(INCS) -I$(RTLOBJD) $(OBJDIR)/pfcache_tb.o $(OBJDIR)/memsim.o $(OBJDIR)/byteswap.o $(VLIB) $(RTLOBJD)/Vpfcache__ALL.a -o $@ + $(CXX) $(CFLAGS) $(VDEFS) $(INCS) -I$(RTLOBJD) $(OBJDIR)/pfcache_tb.o $(OBJDIR)/memsim.o $(OBJDIR)/byteswap.o $(VLIB) $(RTLOBJD)/Vpfcache__ALL.a -lpthread -o $@ pdump: $(ZOBJS) $(OBJDIR)/zopcodes.o $(OBJDIR)/pdump.o pdump: $(ZASM)/zopcodes.h testb.h byteswap.h zipelf.h - $(CXX) $(CFLAGS) $(INCS) $(OBJDIR)/pdump.o $(ZOBJS) -lelf -o $@ + $(CXX) $(CFLAGS) $(INCS) $(OBJDIR)/pdump.o $(ZOBJS) -lelf -lpthread -o $@ .PHONY: stest stest: zipsys_tb diff --git a/sim/verilator/zipcpu_tb.cpp b/sim/verilator/zipcpu_tb.cpp index 5537834..b85fac3 100644 --- a/sim/verilator/zipcpu_tb.cpp +++ b/sim/verilator/zipcpu_tb.cpp @@ -186,9 +186,9 @@ #endif #define early_branch_pc VVAR(_thecpu__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc) -#define dcdRmx VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber15) -#define dcdA VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber15) -#define dcdB VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber16) +// #define dcdRmx VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber15) +#define dcdA VVAR(_thecpu__DOT__full_dcd_A) +#define dcdB VVAR(_thecpu__DOT__full_dcd_B) #define new_pc VVAR(_thecpu__DOT__new_pc) #define cpu_ipc VVAR(_thecpu__DOT__ipc) @@ -225,9 +225,9 @@ #define dcd_opn VVAR(_thecpu__DOT__dcd_opn) #define dcd_rA VVAR(_thecpu__DOT__dcd_rA) #define dcd_rB VVAR(_thecpu__DOT__dcd_rB) -#define dcdR VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR) -#define dcdRpc VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR_pc) -#define dcdRcc VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR_cc) +#define dcdR VVAR(_thecpu__DOT__dcd_preA) +// #define dcdRpc VVAR(_thecpu__DOT__dcd_preA)&0x10 +// #define dcdRcc VVAR(_thecpu__DOT__dcd_preA)&0x20 #define dcd_wR VVAR(_thecpu__DOT__dcd_wR) #define dcd_pc VVAR(_thecpu__DOT__dcd_pc) #define dcd_wF VVAR(_thecpu__DOT__dcd_wF) @@ -302,7 +302,7 @@ #define master_ce VVAR(_thecpu__DOT__master_ce) #define op_break VVAR(_thecpu__DOT__r_op_break) -#define op_F VVAR(_thecpu__DOT__op_F) +#define op_F VVAR(_thecpu__DOT__r_op_F) // #ifdef ROOT_VERILATOR #define regset VVAR(_thecpu__DOT__regset.m_storage)