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Verilog Python Other
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benchmarks
kicad
sim
stat
.gitignore
74_adder.v
74_cmp.v
74_counter.v
74_dffe.v
74_eq.v
74_extract.il
74_extract.v
74_models.v
74_mux.v
74series.lib
bram.rules
equiv.ys
ic_count.py
synth_74.ys
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