Kumar Abhishek edited this page Sep 25, 2015 · 4 revisions

This is the roadmap for the project. The web-frontend is scheduled to begin development post-midterms.

  • Core PRU Firmware & Kernel Module : Ready for first public release
    Features implemented:
    • One-shot or continuous capture
    • Sample depth: as much as RAM available on the BeagleBone Black (400 MB typ)
    • Supported Sample rates: 100 MHz to 100 kHz [100/n MHz, integer n]
    • Samples are 8-bit or 16-bit [only 12-bit or 14-bit(without internal eMMC)]
    • Kernel Module & firmware based on the new remoteproc infrastructure for the PRUs
    • Sample buffer readout through /dev/beaglelogic
      At this stage, the core is fully usable to output the captured binary data via "dd".
  • [o] user-space syscall wrapper for BeagleLogic [libbeaglelogic] : Preliminary
  • sigrok bindings : Done and merged
  • [o] Web frontend & Node.js work : In progress