{"payload":{"header_redesign_enabled":false,"results":[{"id":"76104782","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"aboudou/mojo_fpga_sn74ls49","hl_trunc_description":"An implémentation of SN74LS49 BCD to seven segment decoder logic for Mojo V3 FPGA board","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":76104782,"name":"mojo_fpga_sn74ls49","owner_id":2165241,"owner_login":"aboudou","updated_at":"2016-12-11T06:27:29.955Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":87,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aaboudou%252Fmojo_fpga_sn74ls49%2B","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/aboudou/mojo_fpga_sn74ls49/star":{"post":"EWoO0rwIi-l2FAJf4PI20FqLi8iWv6Dciugsdirzc_v3EZGPBnhBKSPmAACnJsozyTAcTBcvkR4hbC2l0bQfqw"},"/aboudou/mojo_fpga_sn74ls49/unstar":{"post":"MOiP9VO-4lUvq8eYC4i-TlWs-tzYg_rBcEUWqNs6cqqfl2bduumBJpZfqQO5XK61r_pn75OjGJvrwUVzjlL1SQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"6i2ssZ5TPbcVhJKjJWaiW57kn8CHoKYnwOd5pC5DvxtXNs2JLRrmt2vQz3x980MjzgkkgUVM2FdYL1BP2r7yTA"}}},"title":"Repository search results"}