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Add support for Radxa rock 5b #635
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- D pin number is now ordered by physical pin sequence (Instead of BCM) - Changed the peripheral pin name to match the RK3588 datasheet
Typically we wouldn't have pin names for the Mx versions. Instead, you just pass the constructor the pins you want and it'll determine the correct muxing or throw an error. |
But then some peripheral pin, eg.UART2_TX will be corresponding to two pins, and there are no default one. So what to do next? |
I think what Scott meant is that Blinka doesn't usually handle any muxing itself. Often times the device tree that's loaded determines the mux or possibly it may even be set at the kernel level. It's possible to write a specific Pin implementation to mux the pin correctly, but I don't believe there are currently any boards that do this. |
Blinka is meant to be like CircuitPython and in CircuitPython, it is the job of the UART implementation to set the mux for the given mcu pin. Internal peripheral pins aren't referenced in Blinka or CP code. |
Use the lowest MUX index possible.
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Looks good. Thanks for adding.
RK3588 is a recent & very powerful SoC with rich peripherals.
This pull request adds the RK3588 Chip and Rock 5B support.
To prevent confusion since many peripherals pin can be muxed to different GPIOs, the periphal pin name is picked directly from the datasheet, Mx means "Mode x"