diff --git a/ports/esp32s2/esp-idf b/ports/esp32s2/esp-idf index d06744f5efc38..8bc19ba893e55 160000 --- a/ports/esp32s2/esp-idf +++ b/ports/esp32s2/esp-idf @@ -1 +1 @@ -Subproject commit d06744f5efc382c61cbad8758107cec308feef09 +Subproject commit 8bc19ba893e5544d571a753d82b44a84799b94b1 diff --git a/ports/stm/Makefile b/ports/stm/Makefile index b9426e07ec948..89f2452238d57 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -108,6 +108,7 @@ CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align $(ADD_CFLAGS) CFLAGS += -mthumb -mabi=aapcs-linux # Arm core selection +MCU_FLAGS_F1 = -mcpu=cortex-m3 MCU_FLAGS_F4 = -mcpu=cortex-m4 MCU_FLAGS_F7 = -mcpu=cortex-m7 MCU_FLAGS_H7 = -mcpu=cortex-m7 @@ -119,11 +120,12 @@ CFLAGS += -DSTM32_HAL_H='' CFLAGS += -DSTM32_SERIES_LOWER='"stm32$(MCU_SERIES_LOWER)"' # Floating point settings -ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx)) -CFLAGS += -mfpu=fpv5-d16 -mfloat-abi=hard -else -CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard -endif +# ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx)) +# CFLAGS += -mfpu=fpv5-d16 -mfloat-abi=hard +# else +# CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard +# endif +CFLAGS += $(CPU) -mthumb $(FPU) $(FLOAT-ABI) # Need both command and valid file to use uf2 bootloader ifndef LD_FILE @@ -166,19 +168,14 @@ SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ hal_dac.c \ hal_dac_ex.c \ hal_dma.c \ - hal_dma_ex.c \ hal_exti.c \ hal_flash.c \ hal_flash_ex.c \ hal_gpio.c \ hal_i2c.c \ - hal_i2c_ex.c \ hal_pwr.c \ - hal_pwr_ex.c \ - hal_qspi.c \ hal_rcc.c \ hal_rcc_ex.c \ - hal_rng.c \ hal_rtc.c \ hal_rtc_ex.c \ hal_sd.c \ @@ -198,6 +195,17 @@ SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ ll_utils.c \ ) +# The F103 lacks some modules we normally make use of +ifeq ($(MCU_SERIES_LOWER),$(filter $(MCU_SERIES_LOWER),f4 f7 h7)) +SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ + hal_dma_ex.c \ + hal_i2c_ex.c \ + hal_pwr_ex.c \ + hal_qspi.c \ + hal_rng.c \ +) +endif + ifeq ($(CIRCUITPY_CANIO),1) SRC_STM32 += $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_hal_can.c endif @@ -237,6 +245,7 @@ SRC_C += \ ifneq ($(USB),FALSE) SRC_C += lib/tinyusb/src/portable/st/synopsys/dcd_synopsys.c +SRC_C += lib/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c endif SRC_S = \ diff --git a/ports/stm/boards/STM32F103xe_fs.ld b/ports/stm/boards/STM32F103xe_fs.ld new file mode 100644 index 0000000000000..e715b2472d0df --- /dev/null +++ b/ports/stm/boards/STM32F103xe_fs.ld @@ -0,0 +1,26 @@ +/* + GNU linker script for STM32F103 with filesystem +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* bigger than it needs to be, but matches other SoCs */ + FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 112K + FLASH_FIRMWARE (rx) : ORIGIN = 0x08020000, LENGTH = 384K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 24K; +_minimum_heap_size = 16K; + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); diff --git a/ports/stm/boards/stm103re_apm/board.c b/ports/stm/boards/stm103re_apm/board.c new file mode 100644 index 0000000000000..4421970eefe4d --- /dev/null +++ b/ports/stm/boards/stm103re_apm/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/stm/boards/stm103re_apm/mpconfigboard.h b/ports/stm/boards/stm103re_apm/mpconfigboard.h new file mode 100644 index 0000000000000..d4a5a48b8890b --- /dev/null +++ b/ports/stm/boards/stm103re_apm/mpconfigboard.h @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +//Micropython setup + +#define MICROPY_HW_BOARD_NAME "stm103re_apm" +#define MICROPY_HW_MCU_NAME "STM32F103ZE" + +#define HSE_VALUE ((uint32_t)12000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define BOARD_NO_VBUS_SENSE (1) diff --git a/ports/stm/boards/stm103re_apm/mpconfigboard.mk b/ports/stm/boards/stm103re_apm/mpconfigboard.mk new file mode 100644 index 0000000000000..cb54ace32e1cc --- /dev/null +++ b/ports/stm/boards/stm103re_apm/mpconfigboard.mk @@ -0,0 +1,13 @@ +USB_VID = 0x239A +USB_PID = 0x805C +USB_PRODUCT = "APM32F103ze" +USB_MANUFACTURER = "ApexMIC" + +INTERNAL_FLASH_FILESYSTEM = 1 + +MCU_SERIES = F1 +MCU_VARIANT = STM32F103xE +MCU_PACKAGE = LQFP144 + +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F103xe_fs.ld diff --git a/ports/stm/boards/stm103re_apm/pins.c b/ports/stm/boards/stm103re_apm/pins.c new file mode 100644 index 0000000000000..8783dfcf105ab --- /dev/null +++ b/ports/stm/boards/stm103re_apm/pins.c @@ -0,0 +1,52 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR_Y1), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_Y2), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_Y3), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_Y4), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_Y5), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_Y6), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_Y7), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_Y8), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_Y9), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_Y10), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_Y11), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_Y12), MP_ROM_PTR(&pin_PB01) }, + + { MP_ROM_QSTR(MP_QSTR_X1), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_X2), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_X3), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_X4), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_X5), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_X6), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_X7), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_X8), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_X9), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_X10), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_X11), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_X12), MP_ROM_PTR(&pin_PC05) }, + + { MP_ROM_QSTR(MP_QSTR_X17), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_X18), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_X19), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_X20), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_X21), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_X22), MP_ROM_PTR(&pin_PC03) }, + + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_PA13) }, + + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PA13) }, + + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/system_stm32f1xx.c b/ports/stm/boards/system_stm32f1xx.c new file mode 100644 index 0000000000000..9a42ab15b5abe --- /dev/null +++ b/ports/stm/boards/system_stm32f1xx.c @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file system_stm32f1xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f1xx_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE". + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx_system + * @{ + */ + +/** @addtogroup STM32F1xx_System_Private_Includes + * @{ + */ + +#include "stm32f1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM */ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= 0x00000001U; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#if !defined(STM32F105xC) && !defined(STM32F107xC) + RCC->CFGR &= 0xF8FF0000U; +#else + RCC->CFGR &= 0xF0FF0000U; +#endif /* STM32F105xC */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= 0xFF80FFFFU; + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEBFFFFFFU; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000U; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000U; +#elif defined(STM32F100xB) || defined(STM32F100xE) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000U; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000U; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000U; +#endif /* STM32F105xC */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; +#endif /* STM32F105xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) + uint32_t prediv1factor = 0U; +#endif /* STM32F100xB or STM32F100xE */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04U: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08U: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#if !defined(STM32F105xC) && !defined(STM32F107xC) + pllmull = ( pllmull >> 18U) + 2U; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + { + #if defined(STM32F100xB) || defined(STM32F100xE) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18U; + + if (pllmull != 0x0DU) + { + pllmull += 2U; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13U / 2U; + } + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + + if (prediv1source == 0U) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F105xC */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/** + * @brief Setup the external memory controller. Called in startup_stm32f1xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f1xx_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmpreg; + /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); + + (void)(tmpreg); + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; + + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; + + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; + + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index a827399ccb05f..7ede9454b1704 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -41,12 +41,14 @@ #include "supervisor/shared/safe_mode.h" void common_hal_mcu_delay_us(uint32_t delay) { + #if !(CPY_STM32F1) uint32_t ticks_per_us = HAL_RCC_GetSysClockFreq()/1000000; delay *= ticks_per_us; SysTick->LOAD = delay; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {} SysTick->CTRL = 0; + #endif } volatile uint32_t nesting_count = 0; diff --git a/ports/stm/hal_conf/stm32f1xx_hal_conf.h b/ports/stm/hal_conf/stm32f1xx_hal_conf.h new file mode 100644 index 0000000000000..dd39df4d71b05 --- /dev/null +++ b/ports/stm/hal_conf/stm32f1xx_hal_conf.h @@ -0,0 +1,351 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "stm32_hal_conf.h" +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CONF_H +#define __STM32F1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 + +// #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +// #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +// #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +// #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +// #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +// #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +// #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +// #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +// #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +// #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +// #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +// #define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +// #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +// #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +// #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +// #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +// #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +// #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +// #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +// #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +// #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +// #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +// #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32f1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32f1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32f1xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32f1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32f1xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED +#include "stm32f1xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32f1xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32f1xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32f1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32f1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32f1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32f1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32f1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32f1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32f1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32f1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32f1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32f1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32f1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32f1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED +#include "stm32f1xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32f1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32f1xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32f1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32f1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32f1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32f1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32f1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32f1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32f1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32f1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32f1xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32f1xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t* file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif +// CircuitPython specific conditionals. Using a value is better than checking +// defined because undefined variable happen when a file isn't included when it +// should have been. +#define CPY_STM32F1 1 +#endif /* __STM32F1xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index bcecaa517023f..d39c121bd3597 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -11,6 +11,53 @@ ifeq ($(MCU_VARIANT),STM32F405xx) USB_NUM_EP = 4 endif +ifeq ($(MCU_SERIES),F1) + # Typically the second module to create + CIRCUITPY_DIGITALIO = 0 + # Other modules: + CIRCUITPY_ANALOGIO = 0 + CIRCUITPY_BUSIO = 0 + CIRCUITPY_COUNTIO = 0 + CIRCUITPY_NEOPIXEL_WRITE = 0 + CIRCUITPY_PULSEIO = 0 + CIRCUITPY_OS = 0 + CIRCUITPY_NVM = 0 + CIRCUITPY_AUDIOBUSIO = 0 + CIRCUITPY_AUDIOIO = 0 + CIRCUITPY_ROTARYIO = 0 + CIRCUITPY_RTC = 0 + CIRCUITPY_SDCARDIO = 0 + CIRCUITPY_FRAMEBUFFERIO = 0 + CIRCUITPY_FREQUENCYIO = 0 + CIRCUITPY_I2CPERIPHERAL = 0 + # Requires SPI, PulseIO (stub ok): + CIRCUITPY_DISPLAYIO = 0 + + # These modules are implemented in shared-module/ - they can be included in + # any port once their prerequisites in common-hal are complete. + # Requires DigitalIO: + CIRCUITPY_BITBANGIO = 0 + # Requires DigitalIO + CIRCUITPY_GAMEPAD = 0 + # Requires neopixel_write or SPI (dotstar) + CIRCUITPY_PIXELBUF = 0 + # Requires OS + CIRCUITPY_RANDOM = 0 + # Requires OS, filesystem + CIRCUITPY_STORAGE = 0 + # Requires Microcontroller + CIRCUITPY_TOUCHIO = 0 + # Requires USB + CIRCUITPY_USB_HID = 0 + CIRCUITPY_USB_MIDI = 0 + # Does nothing without I2C + CIRCUITPY_REQUIRE_I2C_PULLUPS = 0 + # No requirements, but takes extra flash + CIRCUITPY_ULAB = 0 + + CIRCUITPY_BLEIO_HCI = 0 +endif + ifeq ($(MCU_SERIES),F4) # Not yet implemented common-hal modules: CIRCUITPY_AUDIOBUSIO ?= 0 diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 34089c849ac26..0c12a10ac9858 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -65,6 +65,16 @@ typedef struct { .pin = tim_pin, \ } +// F1 Series +// Access Lines + +#ifdef STM32F103xE +#define HAS_DAC 0 +#define HAS_TRNG 0 +#define HAS_BASIC_TIM 0 +#include "stm32f1/stm32f103xe/periph.h" +#endif + // F4 Series // Access Lines diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index 358313f5651fa..0d61da188a718 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -75,6 +75,10 @@ extern const mp_obj_type_t mcu_pin_type; // Use illegal pin value to mark unassigned pins. #define NO_PIN 0xff +// F1 Series +#ifdef STM32F103xE +#include "stm32f1/stm32f103xe/pins.h" +#endif // F4 Series #ifdef STM32F401xE #include "stm32f4/stm32f401xe/pins.h" diff --git a/ports/stm/peripherals/stm32f1/clocks.c b/ports/stm/peripherals/stm32f1/clocks.c new file mode 100644 index 0000000000000..07f8333b3c2c0 --- /dev/null +++ b/ports/stm/peripherals/stm32f1/clocks.c @@ -0,0 +1,112 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f1xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include + +// F1 Series +#ifdef STM32F103xE +#include "stm32f1/stm32f103xe/clocks.h" +#endif + + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef clkinitstruct = {0}; + RCC_OscInitTypeDef oscinitstruct = {0}; + RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0}; + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + oscinitstruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + oscinitstruct.HSEState = RCC_HSE_ON; + oscinitstruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + oscinitstruct.PLL.PLLMUL = RCC_PLL_MUL9; + oscinitstruct.PLL.PLLState = RCC_PLL_ON; + oscinitstruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + HAL_RCC_OscConfig(&oscinitstruct); + + /* USB clock selection */ + rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB; + rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2; + clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1; + HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2); + + // RCC_ClkInitTypeDef RCC_ClkInitStruct; + // RCC_OscInitTypeDef RCC_OscInitStruct; + // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + // // Set voltage scaling in accordance with system clock speed + // __HAL_RCC_PWR_CLK_ENABLE(); + // //__HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); F1没有 + + // // Set up primary PLL and HSE clocks + // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + // #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + // RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + // RCC_OscInitStruct.LSEState = RCC_LSE_ON; + // #else + // RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + // RCC_OscInitStruct.LSIState = RCC_LSI_ON; + // #endif + // RCC_OscInitStruct.HSEState = RCC_HSE_ON; + // RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; //++++> HSE 一分频 + // RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + // RCC_OscInitStruct.PLL.PLLMUL = CPY_CLK_MUL; //++++> HSE X倍频 + + // if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // // Clock issues are too problematic to even attempt recovery. + // // If you end up here, check whether your LSE settings match your board. + // while(1); + // } + + // // Configure bus clock sources and divisors + // RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + // RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + // RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + // HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // // Set up non-bus peripherals + // // TODO: I2S settings go here + // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + // #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + // PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + // #else + // PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + // #endif + // PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_USB; + // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + // HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +} diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/clocks.h b/ports/stm/peripherals/stm32f1/stm32f103xe/clocks.h new file mode 100644 index 0000000000000..ca9250482ca4a --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/clocks.h @@ -0,0 +1,51 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f1xx_hal.h" + +// Chip: STM32F103 +// Line Type: Foundation Line +// Speed: 72MHz (MAX) + +// Defaults: +// #ifndef CPY_CLK_VSCALE +// #define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +// #endif +#ifndef CPY_CLK_MUL +#define CPY_CLK_MUL (RCC_PLL_MUL9) //倍频选择 +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_2) +#endif diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/gpio.c b/ports/stm/peripherals/stm32f1/stm32f103xe/gpio.c new file mode 100644 index 0000000000000..7eb2a4f6164c8 --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/gpio.c @@ -0,0 +1,54 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "peripherals/gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32_peripherals_gpio_init(void) { + //Enable all GPIO for now + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + //Never reset pins + // never_reset_pin_number(2,13); //PC13 anti tamp + never_reset_pin_number(2,14); //PC14 OSC32_IN + never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(0,13); //PA13 SWDIO + never_reset_pin_number(0,14); //PA14 SWCLK + // never_reset_pin_number(0,15); //PA15 JTDI + // never_reset_pin_number(1,3); //PB3 JTDO + // never_reset_pin_number(1,4); //PB4 JTRST + + // Port H is not included in GPIO port array + // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,1); //PH1 JTRST +} + +void stm32f1_peripherals_status_led(uint8_t led, uint8_t state) { + +} diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/periph.c b/ports/stm/peripherals/stm32f1/stm32f103xe/periph.c new file mode 100644 index 0000000000000..d31c144266c49 --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/periph.c @@ -0,0 +1,192 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" + +// I2C + +I2C_TypeDef * mcu_i2c_banks[2] = {I2C1, I2C2}; + +const mcu_periph_obj_t mcu_i2c_sda_list[3] = { + PERIPH(1, 1, &pin_PB07), + PERIPH(1, 1, &pin_PB09), + PERIPH(2, 1, &pin_PB11), +}; + +const mcu_periph_obj_t mcu_i2c_scl_list[3] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), +}; + +SPI_TypeDef * mcu_spi_banks[3] = {SPI1, SPI2, SPI3}; + +const mcu_periph_obj_t mcu_spi_sck_list[7] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PC07), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 6, &pin_PC10), +}; + +const mcu_periph_obj_t mcu_spi_mosi_list[6] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), +}; + +const mcu_periph_obj_t mcu_spi_miso_list[6] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), +}; + +const mcu_periph_obj_t mcu_spi_nss_list[6] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), +}; + +USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, NULL}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; + +const mcu_periph_obj_t mcu_uart_tx_list[12] = { + PERIPH(4, 8, &pin_PA00), + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), + PERIPH(6, 8, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(4, 8, &pin_PC10), + PERIPH(5, 8, &pin_PC12), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(6, 8, &pin_PG14), +}; + +const mcu_periph_obj_t mcu_uart_rx_list[12] = { + PERIPH(4, 8, &pin_PA01), + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), + PERIPH(6, 8, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(4, 8, &pin_PC11), + PERIPH(5, 8, &pin_PD02), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(6, 8, &pin_PG09), +}; + +//Timers +//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, + NULL, NULL, NULL, NULL}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[56] = { + TIM(2,1,1,&pin_PA00), + TIM(5,2,1,&pin_PA00), + TIM(2,1,2,&pin_PA01), + TIM(5,2,2,&pin_PA01), + TIM(2,1,3,&pin_PA02), + TIM(5,2,3,&pin_PA02), + TIM(2,1,4,&pin_PA03), + TIM(5,2,4,&pin_PA03), + TIM(9,3,1,&pin_PA02), + TIM(9,3,2,&pin_PA03), + TIM(3,2,1,&pin_PA06), + TIM(13,9,1,&pin_PA06), + TIM(3,2,2,&pin_PA07), + TIM(14,9,1,&pin_PA07), + TIM(1,1,1,&pin_PA08), + TIM(1,1,2,&pin_PA09), + TIM(1,1,3,&pin_PA10), + TIM(1,1,4,&pin_PA11), + TIM(2,1,1,&pin_PA15), + TIM(3,2,3,&pin_PB00), + TIM(3,2,4,&pin_PB01), + TIM(2,1,2,&pin_PB03), + TIM(3,2,1,&pin_PB04), + TIM(3,2,2,&pin_PB05), + TIM(4,2,1,&pin_PB06), + TIM(4,2,2,&pin_PB07), + TIM(4,2,3,&pin_PB08), + TIM(10,2,1,&pin_PB08), + TIM(4,2,4,&pin_PB09), + TIM(11,2,1,&pin_PB09), + TIM(2,1,3,&pin_PB10), + TIM(2,1,4,&pin_PB11), + TIM(12,9,1,&pin_PB14), + TIM(12,9,2,&pin_PB15), + TIM(3,2,1,&pin_PC06), + TIM(3,2,2,&pin_PC07), + TIM(3,2,3,&pin_PC08), + TIM(3,2,4,&pin_PC09), + TIM(8,3,1,&pin_PC06), + TIM(8,3,2,&pin_PC07), + TIM(8,3,3,&pin_PC08), + TIM(8,3,4,&pin_PC09), + TIM(4,2,1,&pin_PD12), + TIM(4,2,2,&pin_PD13), + TIM(4,2,3,&pin_PD14), + TIM(4,2,4,&pin_PD15), + TIM(9,3,1,&pin_PE05), + TIM(9,3,2,&pin_PE06), + TIM(1,1,1,&pin_PE09), + TIM(1,1,2,&pin_PE11), + TIM(1,1,3,&pin_PE13), + TIM(1,1,4,&pin_PE14), + TIM(10,3,1,&pin_PF06), + TIM(11,3,1,&pin_PF07), + TIM(13,9,1,&pin_PF08), + TIM(14,9,1,&pin_PF09), + // TIM(12,9,1,&pin_PH06), //TODO: include these when pin map is expanded + // TIM(12,9,2,&pin_PH09), + // TIM(5,2,1,&pin_PH10), + // TIM(5,2,2,&pin_PH11), + // TIM(5,2,3,&pin_PH12), + // TIM(5,2,4,&pin_PI00), + // TIM(8,3,4,&pin_PI02), + // TIM(8,3,1,&pin_PI05), + // TIM(8,3,2,&pin_PI06), + // TIM(8,3,3,&pin_PI07), +}; diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/periph.h b/ports/stm/peripherals/stm32f1/stm32f103xe/periph.h new file mode 100644 index 0000000000000..a3da52920b3a7 --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/periph.h @@ -0,0 +1,57 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H + +//I2C +extern I2C_TypeDef * mcu_i2c_banks[2]; + +extern const mcu_periph_obj_t mcu_i2c_sda_list[3]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[3]; + +//SPI +extern SPI_TypeDef * mcu_spi_banks[3]; + +extern const mcu_periph_obj_t mcu_spi_sck_list[7]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[6]; +extern const mcu_periph_obj_t mcu_spi_miso_list[6]; +extern const mcu_periph_obj_t mcu_spi_nss_list[6]; + +//UART +extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; + +extern const mcu_periph_obj_t mcu_uart_tx_list[12]; +extern const mcu_periph_obj_t mcu_uart_rx_list[12]; + +//Timers +#define TIM_BANK_ARRAY_LEN 14 +#define TIM_PIN_ARRAY_LEN 56 +TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/pins.c b/ports/stm/peripherals/stm32f1/stm32f103xe/pins.c new file mode 100644 index 0000000000000..4282741a84582 --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/pins.c @@ -0,0 +1,161 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" + +const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); +const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); +const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); +const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); +const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); + +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT + +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only + +const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_123,10)); +const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_123,11)); +const mcu_pin_obj_t pin_PC02 = PIN(2, 2, ADC_INPUT(ADC_123,12)); +const mcu_pin_obj_t pin_PC03 = PIN(2, 3, ADC_INPUT(ADC_123,13)); + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_123,0)); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_123,1)); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_123,2)); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_123,3)); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_12,4)); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_12,5)); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_12,6)); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_12,7)); + +const mcu_pin_obj_t pin_PC04 = PIN(2, 4, ADC_INPUT(ADC_12,14)); +const mcu_pin_obj_t pin_PC05 = PIN(2, 5, ADC_INPUT(ADC_12,15)); + +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_12,8)); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_12,9)); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); //BOOT1 + +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); +const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); +const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); +const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); +const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); +const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); +const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); +const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); +const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); + +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); + +const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); +const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); +const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); +const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); +const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); +const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); +const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); +const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); + +const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); +const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); +const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); +const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); + +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); + +const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); +const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); +const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); + +const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); +const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); +const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); +const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); +const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); +const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); +const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); +const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); + +const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); + +const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f1/stm32f103xe/pins.h b/ports/stm/peripherals/stm32f1/stm32f103xe/pins.h new file mode 100644 index 0000000000000..e722b6e5ae37a --- /dev/null +++ b/ports/stm/peripherals/stm32f1/stm32f103xe/pins.h @@ -0,0 +1,158 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H + +//Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only +//pg 50 +extern const mcu_pin_obj_t pin_PE02; +extern const mcu_pin_obj_t pin_PE03; +extern const mcu_pin_obj_t pin_PE04; +extern const mcu_pin_obj_t pin_PE05; +extern const mcu_pin_obj_t pin_PE06; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +//pg 51 +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only +//pg 52 +extern const mcu_pin_obj_t pin_PC00; +extern const mcu_pin_obj_t pin_PC01; +extern const mcu_pin_obj_t pin_PC02; +extern const mcu_pin_obj_t pin_PC03; +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +//pg 53 +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PC04; +//pg 54 +extern const mcu_pin_obj_t pin_PC05; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only +//pg 55 +extern const mcu_pin_obj_t pin_PE07; +extern const mcu_pin_obj_t pin_PE08; +extern const mcu_pin_obj_t pin_PE09; +extern const mcu_pin_obj_t pin_PE10; +extern const mcu_pin_obj_t pin_PE11; +extern const mcu_pin_obj_t pin_PE12; +extern const mcu_pin_obj_t pin_PE13; +extern const mcu_pin_obj_t pin_PE14; +//pg 56 +extern const mcu_pin_obj_t pin_PE15; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; // 144 only +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +//pg 57 +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PD08; +extern const mcu_pin_obj_t pin_PD09; +extern const mcu_pin_obj_t pin_PD10; +extern const mcu_pin_obj_t pin_PD11; +extern const mcu_pin_obj_t pin_PD12; +//pg 58 +extern const mcu_pin_obj_t pin_PD13; +extern const mcu_pin_obj_t pin_PD14; +extern const mcu_pin_obj_t pin_PD15; +extern const mcu_pin_obj_t pin_PG02; // 144 only +extern const mcu_pin_obj_t pin_PG03; // 144 only +extern const mcu_pin_obj_t pin_PG04; // 144 only +extern const mcu_pin_obj_t pin_PG05; // 144 only +extern const mcu_pin_obj_t pin_PG06; // 144 only +extern const mcu_pin_obj_t pin_PG07; // 144 only +extern const mcu_pin_obj_t pin_PG08; // 144 only +//pg 59 +extern const mcu_pin_obj_t pin_PC06; +extern const mcu_pin_obj_t pin_PC07; +extern const mcu_pin_obj_t pin_PC08; +extern const mcu_pin_obj_t pin_PC09; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +//pg 60 +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PC10; +extern const mcu_pin_obj_t pin_PC11; +//pg 61 +extern const mcu_pin_obj_t pin_PC12; +extern const mcu_pin_obj_t pin_PD00; +extern const mcu_pin_obj_t pin_PD01; +extern const mcu_pin_obj_t pin_PD02; +extern const mcu_pin_obj_t pin_PD03; +extern const mcu_pin_obj_t pin_PD04; +extern const mcu_pin_obj_t pin_PD05; +extern const mcu_pin_obj_t pin_PD06; +extern const mcu_pin_obj_t pin_PD07; +//pg 62 +extern const mcu_pin_obj_t pin_PG09; // 144 only +extern const mcu_pin_obj_t pin_PG10; // 144 only +extern const mcu_pin_obj_t pin_PG11; // 144 only +extern const mcu_pin_obj_t pin_PG12; // 144 only +extern const mcu_pin_obj_t pin_PG13; // 144 only +extern const mcu_pin_obj_t pin_PG14; // 144 only +extern const mcu_pin_obj_t pin_PG15; // 144 only +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +//pg 63 +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PE00; +extern const mcu_pin_obj_t pin_PE01; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 78ee4f3e605d4..b7c45af454a32 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -49,9 +49,14 @@ typedef struct { /*------------------------------------------------------------------*/ /* Internal Flash API *------------------------------------------------------------------*/ +#if defined(STM32F1) + STATIC const flash_layout_t flash_layout[] = { + // F103: 0x8000000, 0x800 (2kb), 255 + { FLASH_BASE, FLASH_PAGE_SIZE, (FLASH_BANK1_END + 1 - FLASH_BASE) / FLASH_PAGE_SIZE }, + }; + STATIC uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); -#if defined(STM32F4) - +#elif defined(STM32F4) STATIC const flash_layout_t flash_layout[] = { { 0x08000000, 0x04000, 4 }, { 0x08010000, 0x10000, 1 }, @@ -68,7 +73,6 @@ typedef struct { STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); #elif defined(STM32F7) - // FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to // FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7 #define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR @@ -87,8 +91,8 @@ typedef struct { }; STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4))); #endif -#elif defined(STM32H7) +#elif defined(STM32H7) STATIC const flash_layout_t flash_layout[] = { { 0x08000000, 0x20000, 16 }, }; @@ -162,27 +166,39 @@ uint32_t supervisor_flash_get_block_count(void) { } void port_internal_flash_flush(void) { + if (_cache_flash_addr == NO_CACHE) return; - #if defined(STM32H7) + #if defined(STM32F1) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + #elif defined(STM32H7) __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2); #else __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); #endif - // set up for erase + // Set parameters for erase FLASH_EraseInitTypeDef EraseInitStruct; - EraseInitStruct.TypeErase = TYPEERASE_SECTORS; - EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V - // get the sector information uint32_t sector_size; uint32_t sector_start_addr = 0xffffffff; - #if defined(STM32H7) - EraseInitStruct.Banks = get_bank(_cache_flash_addr); + + #if defined(STM32F1) + // F1 pages are referred to as sectors outside this section for simplicity + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); + EraseInitStruct.PageAddress = sector_start_addr; + EraseInitStruct.NbPages = 1; + #else + EraseInitStruct.TypeErase = TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V + #if defined(STM32H7) + EraseInitStruct.Banks = get_bank(_cache_flash_addr); + #endif + EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); + EraseInitStruct.NbSectors = 1; #endif - EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); - EraseInitStruct.NbSectors = 1; + if (sector_size > sizeof(_flash_cache) || sector_start_addr == 0xffffffff) { reset_into_safe_mode(FLASH_WRITE_FAIL); } @@ -203,32 +219,32 @@ void port_internal_flash_flush(void) { uint32_t * cache_addr = (uint32_t*)_flash_cache; #if defined(STM32H7) - for (uint32_t i = 0; i < (sector_size / 32); i++) { - // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr, - (uint32_t)cache_addr) != HAL_OK) { - // error occurred during flash write - HAL_FLASH_Lock(); // lock the flash - reset_into_safe_mode(FLASH_WRITE_FAIL); + // Program in 256 bit flash words + for (uint32_t i = 0; i < (sector_size / 32); i++) { + // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr, + (uint32_t)cache_addr) != HAL_OK) { + // error occurred during flash write + HAL_FLASH_Lock(); // lock the flash + reset_into_safe_mode(FLASH_WRITE_FAIL); + } + // RAM memory is by word (4 byte), but flash memory is by byte + cache_addr += 8; + sector_start_addr += 32; } - // RAM memory is by word (4 byte), but flash memory is by byte - cache_addr += 8; - sector_start_addr += 32; - } - - #else // STM32F4 - // program the flash word by word - for (uint32_t i = 0; i < sector_size / 4; i++) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr, - (uint64_t)*cache_addr) != HAL_OK) { - // error occurred during flash write - HAL_FLASH_Lock(); // lock the flash - reset_into_safe_mode(FLASH_WRITE_FAIL); + #else // STM32 F1, F4, F7 + // Program in 32 bit words + for (uint32_t i = 0; i < sector_size / 4; i++) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr, + (uint64_t)*cache_addr) != HAL_OK) { + // error occurred during flash write + HAL_FLASH_Lock(); // lock the flash + reset_into_safe_mode(FLASH_WRITE_FAIL); + } + // RAM memory is by word (4 byte), but flash memory is by byte + cache_addr += 1; + sector_start_addr += 4; } - // RAM memory is by word (4 byte), but flash memory is by byte - cache_addr += 1; - sector_start_addr += 4; - } #endif // lock the flash @@ -275,6 +291,7 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { while (num_blocks) { + int32_t dest = convert_block_to_flash_addr(block_num); if (dest == -1) { // bad block number @@ -293,17 +310,15 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, reset_into_safe_mode(FLASH_WRITE_FAIL); } - // Find how many blocks are left in the sector + // If our list of blocks goes over a sector boundary, we do this while loop again, + // so only count up to the end of the sector at maximum uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; count = MIN(num_blocks, count); + // if the cache points at the wrong sector, flush it and copy the new one if (_cache_flash_addr != sector_start_addr) { - // Write out anything in cache before overwriting it. supervisor_flash_flush(); - _cache_flash_addr = sector_start_addr; - - // Copy the current contents of the entire page into the cache. memcpy(_flash_cache, (void *)sector_start_addr, sector_size); } diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 19ae03e0b3dd0..c92ed133d2d06 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -32,6 +32,11 @@ #include #include "py/mpconfig.h" +#ifdef STM32F103xE +#define STM32_FLASH_SIZE 0x80000 //512KiB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x1C000 //112KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#endif #ifdef STM32F401xE #define STM32_FLASH_SIZE 0x80000 //512KiB diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index a8aab00ff25e3..cec770f32ffec 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -160,13 +160,15 @@ __attribute__((used, naked)) void Reset_Handler(void) { // Low power clock variables static volatile uint32_t systick_ms; -static RTC_HandleTypeDef _hrtc; +#if !(CPY_STM32F1) +static RTC_HandleTypeDef _hrtc; #if BOARD_HAS_LOW_SPEED_CRYSTAL static uint32_t rtc_clock_frequency = LSE_VALUE; #else static uint32_t rtc_clock_frequency = LSI_VALUE; #endif +#endif safe_mode_t port_init(void) { HAL_Init(); // Turns on SysTick @@ -179,8 +181,10 @@ safe_mode_t port_init(void) { stm32_peripherals_clocks_init(); stm32_peripherals_gpio_init(); - // RTC oscillator selection is handled in peripherals///clocks.c + #if !(CPY_STM32F1) __HAL_RCC_RTC_ENABLE(); + + // RTC oscillator selection is handled in peripherals///clocks.c _hrtc.Instance = RTC; _hrtc.Init.HourFormat = RTC_HOURFORMAT_24; // Divide async as little as possible so that we have rtc_clock_frequency count in subseconds. @@ -188,13 +192,15 @@ safe_mode_t port_init(void) { _hrtc.Init.AsynchPrediv = 0x0; _hrtc.Init.SynchPrediv = rtc_clock_frequency - 1; _hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; - HAL_RTC_Init(&_hrtc); HAL_RTCEx_EnableBypassShadow(&_hrtc); HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); // Turn off SysTick SysTick->CTRL = 0; + #else + SysTick_Config(SystemCoreClock / 1000); + #endif return NO_SAFE_MODE; } @@ -329,6 +335,7 @@ volatile uint32_t cached_date = 0; volatile uint32_t seconds_to_minute = 0; volatile uint32_t cached_hours_minutes = 0; uint64_t port_get_raw_ticks(uint8_t* subticks) { + #if !(CPY_STM32F1) // Disable IRQs to ensure we read all of the RTC registers as close in time as possible. Read // SSR twice to make sure we didn't read across a tick. __disable_irq(); @@ -374,37 +381,49 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) { uint64_t raw_ticks = ((uint64_t) 1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32; return raw_ticks; + #else + return systick_ms; + #endif } void RTC_WKUP_IRQHandler(void) { + #if !(CPY_STM32F1) supervisor_tick(); __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&_hrtc, RTC_FLAG_WUTF); __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + #endif } volatile bool alarmed_already = false; void RTC_Alarm_IRQHandler(void) { + #if !(CPY_STM32F1) HAL_RTC_DeactivateAlarm(&_hrtc, RTC_ALARM_A); __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); __HAL_RTC_ALARM_CLEAR_FLAG(&_hrtc, RTC_FLAG_ALRAF); alarmed_already = true; + #endif } // Enable 1/1024 second tick. void port_enable_tick(void) { + #if !(CPY_STM32F1) HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, rtc_clock_frequency / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2); HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 1, 0U); HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + #endif } extern volatile uint32_t autoreload_delay_ms; // Disable 1/1024 second tick. void port_disable_tick(void) { + #if !(CPY_STM32F1) HAL_NVIC_DisableIRQ(RTC_WKUP_IRQn); HAL_RTCEx_DeactivateWakeUpTimer(&_hrtc); + #endif } void port_interrupt_after_ticks(uint32_t ticks) { + #if !(CPY_STM32F1) uint64_t raw_ticks = port_get_raw_ticks(NULL) + ticks; RTC_AlarmTypeDef alarm; @@ -434,9 +453,11 @@ void port_interrupt_after_ticks(uint32_t ticks) { HAL_RTC_SetAlarm_IT(&_hrtc, &alarm, RTC_FORMAT_BIN); alarmed_already = false; + #endif } void port_sleep_until_interrupt(void) { + #if !(CPY_STM32F1) // Clear the FPU interrupt because it can prevent us from sleeping. if (__get_FPSCR() & ~(0x9f)) { __set_FPSCR(__get_FPSCR() & ~(0x9f)); @@ -446,6 +467,7 @@ void port_sleep_until_interrupt(void) { return; } __WFI(); + #endif } // Required by __libc_init_array in startup code if we are compiling using diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index c0e012cc625e9..ff800b32dbabe 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -35,8 +35,8 @@ #include "common-hal/microcontroller/Pin.h" +#if !CPY_STM32F1 STATIC void init_usb_vbus_sense(void) { - #if (BOARD_NO_VBUS_SENSE) // Disable VBUS sensing #ifdef USB_OTG_GCCFG_VBDEN @@ -61,6 +61,7 @@ STATIC void init_usb_vbus_sense(void) { #endif #endif } +#endif void init_usb_hardware(void) { //TODO: if future chips overload this with options, move to peripherals management. @@ -73,67 +74,98 @@ void init_usb_hardware(void) { */ __HAL_RCC_GPIOA_CLK_ENABLE(); - /* Configure DM DP Pins */ - GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - #if CPY_STM32H7 - GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif CPY_STM32F4 || CPY_STM32F7 - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - #endif - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - never_reset_pin_number(0, 11); - never_reset_pin_number(0, 12); - claim_pin(0, 11); - claim_pin(0, 12); - - /* Configure VBUS Pin */ - #if !(BOARD_NO_VBUS_SENSE) - GPIO_InitStruct.Pin = GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - never_reset_pin_number(0, 9); - claim_pin(0, 9); - #endif + #if CPY_STM32F1 + GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + #else + /* Configure DM DP Pins */ + GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + #if CPY_STM32H7 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + #elif CPY_STM32F4 || CPY_STM32F7 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #endif + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + never_reset_pin_number(0, 11); + never_reset_pin_number(0, 12); + claim_pin(0, 11); + claim_pin(0, 12); + + /* Configure VBUS Pin */ + #if !(BOARD_NO_VBUS_SENSE) + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + never_reset_pin_number(0, 9); + claim_pin(0, 9); + #endif + + /* This for ID line debug */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + #if CPY_STM32H7 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + #elif CPY_STM32F4 || CPY_STM32F7 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #endif + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + never_reset_pin_number(0, 10); + claim_pin(0, 10); + + #ifdef STM32F412Zx + /* Configure POWER_SWITCH IO pin (F412 ONLY)*/ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + never_reset_pin_number(0, 8); + claim_pin(0, 8); + #endif - /* This for ID line debug */ - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - #if CPY_STM32H7 - GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif CPY_STM32F4 || CPY_STM32F7 - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - #endif - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - never_reset_pin_number(0, 10); - claim_pin(0, 10); - - #ifdef STM32F412Zx - /* Configure POWER_SWITCH IO pin (F412 ONLY)*/ - GPIO_InitStruct.Pin = GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - never_reset_pin_number(0, 8); - claim_pin(0, 8); #endif - #if CPY_STM32H7 + + #if CPY_STM32F1 + // NVIC_SetPriority(USB_HP_CAN1_TX_IRQn, 15); + // NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 15); + // NVIC_SetPriority(USBWakeUp_IRQn, 15); + __HAL_RCC_USB_CLK_ENABLE(); + // FS USB only does not do voltage sensing. + #elif CPY_STM32H7 HAL_PWREx_EnableUSBVoltageDetector(); __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); + init_usb_vbus_sense(); #else /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - #endif - init_usb_vbus_sense(); + #endif } void OTG_FS_IRQHandler(void) { usb_irq_handler(); } + +void USB_HP_IRQHandler(void) +{ + tud_int_handler(0); +} + +void USB_LP_IRQHandler(void) +{ + tud_int_handler(0); +} + +void USBWakeUp_IRQHandler(void) +{ + tud_int_handler(0); +}