From 542ee4842530780c979826bb0032000ff17fed7d Mon Sep 17 00:00:00 2001 From: Dan Halbert Date: Sat, 18 Nov 2023 15:05:50 -0500 Subject: [PATCH 1/9] Fix USB PID for arduino_nano_esp32s3 --- ports/espressif/boards/arduino_nano_esp32s3/mpconfigboard.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/espressif/boards/arduino_nano_esp32s3/mpconfigboard.mk b/ports/espressif/boards/arduino_nano_esp32s3/mpconfigboard.mk index c9af3af25e73a..925c4ab6e2c65 100644 --- a/ports/espressif/boards/arduino_nano_esp32s3/mpconfigboard.mk +++ b/ports/espressif/boards/arduino_nano_esp32s3/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x2341 -USB_PID = 0x0070 +USB_PID = 0x056B USB_PRODUCT = "Arduino Nano ESP32" USB_MANUFACTURER = "Arduino" From 19dcbe3e01b7f1d1630326f519663056e62a77e3 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 21 Nov 2023 21:15:14 -0600 Subject: [PATCH 2/9] add another flash chip for hallowing m0 express A small number of hallowing m0 express boards were manufactured with an incorrect flash chip (2MB instead of 8MB). If you have received one of these boards, contact support AT adafruit DOT com for refund/replacement options. However, there's no need to make these boards e-waste. At the cost of a few bytes of flash, we can make them work with this simple update, as tested by a user who received one of the incorrectly manufactured units. --- ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.mk b/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.mk index 1c032f02c09cb..b9ff92f470564 100644 --- a/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.mk +++ b/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.mk @@ -7,7 +7,7 @@ CHIP_VARIANT = SAMD21G18A CHIP_FAMILY = samd21 SPI_FLASH_FILESYSTEM = 1 -EXTERNAL_FLASH_DEVICES = "W25Q64JVxQ, GD25Q64C" +EXTERNAL_FLASH_DEVICES = "W25Q64JVxQ, GD25Q64C, W25Q16JVxQ" LONGINT_IMPL = NONE # To keep the build small From 9146f8964fb1443b52b32fb18301f871a96930fe Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Mon, 27 Nov 2023 16:15:12 -0500 Subject: [PATCH 3/9] initial dck01 board (not working) --- ports/raspberrypi/boards/dck01/board.c | 215 ++++++++++++++++++ .../raspberrypi/boards/dck01/mpconfigboard.h | 19 ++ .../raspberrypi/boards/dck01/mpconfigboard.mk | 15 ++ .../boards/dck01/pico-sdk-configboard.h | 1 + ports/raspberrypi/boards/dck01/pins.c | 97 ++++++++ 5 files changed, 347 insertions(+) create mode 100644 ports/raspberrypi/boards/dck01/board.c create mode 100644 ports/raspberrypi/boards/dck01/mpconfigboard.h create mode 100644 ports/raspberrypi/boards/dck01/mpconfigboard.mk create mode 100644 ports/raspberrypi/boards/dck01/pico-sdk-configboard.h create mode 100644 ports/raspberrypi/boards/dck01/pins.c diff --git a/ports/raspberrypi/boards/dck01/board.c b/ports/raspberrypi/boards/dck01/board.c new file mode 100644 index 0000000000000..1853a710426b0 --- /dev/null +++ b/ports/raspberrypi/boards/dck01/board.c @@ -0,0 +1,215 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2021 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. + + +#include "supervisor/board.h" +#include "supervisor/shared/board.h" +#include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/busio/SPI.h" +#include "shared-bindings/displayio/FourWire.h" +// #include "shared-bindings/time/__init__.h" +#include "shared-module/displayio/__init__.h" +// #include "shared-module/displayio/mipi_constants.h" + +displayio_fourwire_obj_t board_display_obj; + +#define HEIGHT 200 +#define WIDTH 200 + +#define DELAY 0x80 + +#define EPD_RAM_BW 0x10 +#define EPD_RAM_RED 0x13 +#define BUSY_WAIT 500 + +// These commands are the combination of SSD1608 and SSD1681 and not all commands are supported for each controller +#define SSD_DRIVER_CONTROL 0x01 +#define SSD_GATE_VOLTAGE 0x03 +#define SSD_SOURCE_VOLTAGE 0x04 +#define SSD_DISPLAY_CONTROL 0x07 +#define SSD_PROGOTP_INITIAL 0x08 +#define SSD_PROGREG_INITIAL 0x09 +#define SSD_READREG_INITIAL 0x0A +#define SSD_NON_OVERLAP 0x0B +#define SSD_BOOST_SOFT_START 0x0C +#define SSD_DEEP_SLEEP 0x10 +#define SSD_DATA_MODE 0x11 +#define SSD_SW_RESET 0x12 +#define SSD1681_TEMP_CONTROL 0x18 +#define SSD1608_TEMP_CONTROL 0x1C +#define SSD_TEMP_WRITE 0x1A +#define SSD_TEMP_READ 0x1B +#define SSD_MASTER_ACTIVATE 0x20 +#define SSD_DISP_CTRL1 0x21 +#define SSD_DISP_CTRL2 0x22 +#define SSD_WRITE_RAM1 0x24 +#define SSD_READ_RAM1 0x24 +#define SSD_WRITE_RAM2 0x26 +#define SSD_READ_RAM2 0x24 +#define SSD_WRITE_VCOM 0x2C +#define SSD_READ_OTP 0x2D +#define SSD_READ_STATUS 0x2F +#define SSD_WRITE_LUT 0x32 +#define SSD_WRITE_DUMMY 0x3A +#define SSD1608_WRITE_GATELINE 0x3B +#define SSD_WRITE_BORDER 0x3C +#define SSD_SET_RAMXPOS 0x44 +#define SSD_SET_RAMYPOS 0x45 +#define SSD_SET_RAMXCOUNT 0x4E +#define SSD_SET_RAMYCOUNT 0x4F +#define SSD_NOP 0xFF + + +#if 1 // SSD1608 + +#define SSD_TEMP_CONTROL SSD1608_TEMP_CONTROL + +const uint8_t _start_sequence[] = { + SSD_SW_RESET, 0, // soft reset + SSD_NOP, 20, // busy wait 20ms + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00, // set display size + SSD_WRITE_DUMMY, 1, 0x1b, // Set dummy line period + SSD1608_WRITE_GATELINE, 1, 0x0b, // Set gate line width + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + SSD_SET_RAMXPOS, 1, 0x00, + SSD_SET_RAMYPOS, 2, 0x00, 0x00, + SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage + SSD_WRITE_LUT, 30, 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, 0x69, 0x59, 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT + SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes + SSD_NOP, 20, // busy wait +}; + +const uint8_t _stop_sequence[] = { + SSD_DEEP_SLEEP, 1, 0x01 // Enter deep sleep +}; + +const uint8_t _refresh_sequence[] = { + SSD_SW_RESET, 0, // soft reset +}; + +#else // SD1681 + +#define SSD_TEMP_CONTROL SSD1681_TEMP_CONTROL + +const uint8_t _start_sequence[] = { + SSD_SW_RESET,, 0x80, 20, // soft reset and wait 20ms + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + SSD_SET_RAMXPOS, 1, 0x00, + SSD_SET_RAMYPOS, 2, 0x00, 0x00, + SSD_WRITE_BORDER, 1, 0x05 // border color + SSD_TEMP_CONTROL, 1, 0x80, // Temp control + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00 // set display size + SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes +}; + +const uint8_t _stop_sequence[] = { + SSD_DEEP_SLEEP, 0x81, 1, 0x64 // Enter deep sleep +}; + +const uint8_t _refresh_sequence[] = { + SSD_SW_RESET, 0, // soft reset +}; + +#endif // EPD choice + + +void board_init(void) { + displayio_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus; + busio_spi_obj_t *spi = &bus->inline_bus; + + common_hal_busio_spi_construct(spi, DEFAULT_SPI_BUS_SCK, DEFAULT_SPI_BUS_MOSI, NULL, false); + common_hal_busio_spi_never_reset(spi); + + // Set up the DisplayIO pin object + bus->base.type = &displayio_fourwire_type; + + common_hal_displayio_fourwire_construct( + bus, + spi, + DEFAULT_SPI_BUS_DC, // EPD_DC Command or data + DEFAULT_SPI_BUS_CS, // EPD_CS Chip select + DEFAULT_SPI_BUS_RESET, // EPD_RST Reset + 1200000, // Baudrate + 0, // Polarity + 0); // Phase + + // Set up the DisplayIO epaper object + displayio_epaperdisplay_obj_t *display = &allocate_display()->epaper_display; + display->base.type = &displayio_epaperdisplay_type; + + common_hal_displayio_epaperdisplay_construct( + display, + bus, + _start_sequence, + sizeof(_start_sequence), + 0, // start up time + _stop_sequence, + sizeof(_stop_sequence), + WIDTH, // width + HEIGHT, // height + WIDTH, // RAM width + HEIGHT, // RAM height + 0, // colstart + 0, // rowstart + 0, // rotation + NO_COMMAND, // set_column_window_command + NO_COMMAND, // set_row_window_command + NO_COMMAND, // set_current_column_command + NO_COMMAND, // set_current_row_command + 0x13, // write_black_ram_command + false, // black_bits_inverted + NO_COMMAND, // write_color_ram_command (can add this for grayscale eventually) + false, // color_bits_inverted + 0x000000, // highlight_color + _refresh_sequence, // refresh_display_sequence + sizeof(_refresh_sequence), + 45, // refresh_time (seconds) + DEFAULT_SPI_BUS_BUSY, // busy_pin + false, // busy_state + 5, // seconds_per_frame (minimum and Adafruit recommends 180) + false, // chip_select (don't always toggle chip select) + false, // grayscale + false, // acep + false, // two_byte_sequence_length + false // address_little_endian + ); +} + + +void board_deinit(void) { + displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; + if (display->base.type == &displayio_epaperdisplay_type) { + while (common_hal_displayio_epaperdisplay_get_busy(display)) { + RUN_BACKGROUND_TASKS; + } + } + common_hal_displayio_release_displays(); +} + +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.h b/ports/raspberrypi/boards/dck01/mpconfigboard.h new file mode 100644 index 0000000000000..5279961a84e2c --- /dev/null +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.h @@ -0,0 +1,19 @@ +#define MICROPY_HW_BOARD_NAME "RP2040 DCK01" +#define MICROPY_HW_MCU_NAME "rp2040" + +#define MICROPY_HW_LED_STATUS (&pin_GPIO4) +#define MICROPY_HW_NEOPIXEL (&pin_GPIO5) + +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO3) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO2) + +#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO9) +#define DEFAULT_SPI_BUS_RESET (&pin_GPIO10) +#define DEFAULT_SPI_BUS_DC (&pin_GPIO11) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) +#define DEFAULT_SPI_BUS_CS (&pin_GPIO13) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) + +#define DEFAULT_UART_BUS_RX (&pin_GPIO1) +#define DEFAULT_UART_BUS_TX (&pin_GPIO0) diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.mk b/ports/raspberrypi/boards/dck01/mpconfigboard.mk new file mode 100644 index 0000000000000..268b452d28fe1 --- /dev/null +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.mk @@ -0,0 +1,15 @@ +USB_VID = 0x1209 +USB_PID = 0xA182 +USB_PRODUCT = "RP2040 DCK01" +USB_MANUFACTURER = "Bradán Lane STUDIO" +CHIP_VARIANT = RP2040 +CHIP_FAMILY = rp2 + +EXTERNAL_FLASH_DEVICES = "GD25Q64C" + +CIRCUITPY__EVE = 1 + +FROZEN_MPY_DIRS += $(TOP)/ports/raspberrypi/boards/dck01 +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_HID +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Register diff --git a/ports/raspberrypi/boards/dck01/pico-sdk-configboard.h b/ports/raspberrypi/boards/dck01/pico-sdk-configboard.h new file mode 100644 index 0000000000000..36da55d457197 --- /dev/null +++ b/ports/raspberrypi/boards/dck01/pico-sdk-configboard.h @@ -0,0 +1 @@ +// Put board-specific pico-sdk definitions here. This file must exist. diff --git a/ports/raspberrypi/boards/dck01/pins.c b/ports/raspberrypi/boards/dck01/pins.c new file mode 100644 index 0000000000000..c811477ecf0ad --- /dev/null +++ b/ports/raspberrypi/boards/dck01/pins.c @@ -0,0 +1,97 @@ +#include "shared-bindings/board/__init__.h" +#include "supervisor/board.h" +#include "shared-module/displayio/__init__.h" + + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS + + + { MP_ROM_QSTR(MP_QSTR_GP0), MP_ROM_PTR(&pin_GPIO0) }, + { MP_ROM_QSTR(MP_QSTR_GP1), MP_ROM_PTR(&pin_GPIO1) }, + + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO0) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO1) }, + + + { MP_ROM_QSTR(MP_QSTR_GP2), MP_ROM_PTR(&pin_GPIO2) }, + { MP_ROM_QSTR(MP_QSTR_GP3), MP_ROM_PTR(&pin_GPIO3) }, + + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO2) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO3) }, + + + { MP_ROM_QSTR(MP_QSTR_GP4), MP_ROM_PTR(&pin_GPIO4) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) }, + + + { MP_ROM_QSTR(MP_QSTR_GP5), MP_ROM_PTR(&pin_GPIO5) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO5) }, + + + { MP_ROM_QSTR(MP_QSTR_GP6), MP_ROM_PTR(&pin_GPIO6) }, + { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPIO6) }, + + + { MP_ROM_QSTR(MP_QSTR_GP7), MP_ROM_PTR(&pin_GPIO7) }, + { MP_ROM_QSTR(MP_QSTR_GP8), MP_ROM_PTR(&pin_GPIO8) }, + { MP_ROM_QSTR(MP_QSTR_GP9), MP_ROM_PTR(&pin_GPIO9) }, + { MP_ROM_QSTR(MP_QSTR_GP10), MP_ROM_PTR(&pin_GPIO10) }, + { MP_ROM_QSTR(MP_QSTR_GP11), MP_ROM_PTR(&pin_GPIO11) }, + + + { MP_ROM_QSTR(MP_QSTR_GP12), MP_ROM_PTR(&pin_GPIO12) }, + { MP_ROM_QSTR(MP_QSTR_GP13), MP_ROM_PTR(&pin_GPIO13) }, + { MP_ROM_QSTR(MP_QSTR_GP14), MP_ROM_PTR(&pin_GPIO14) }, + { MP_ROM_QSTR(MP_QSTR_GP15), MP_ROM_PTR(&pin_GPIO15) }, + + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO12) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO14) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO15) }, + + + { MP_ROM_QSTR(MP_QSTR_GP16), MP_ROM_PTR(&pin_GPIO16) }, + { MP_ROM_QSTR(MP_QSTR_GP17), MP_ROM_PTR(&pin_GPIO17) }, + { MP_ROM_QSTR(MP_QSTR_GP18), MP_ROM_PTR(&pin_GPIO18) }, + { MP_ROM_QSTR(MP_QSTR_I2S_DATA), MP_ROM_PTR(&pin_GPIO16) }, + { MP_ROM_QSTR(MP_QSTR_I2S_BIT_CLOCK), MP_ROM_PTR(&pin_GPIO17) }, + { MP_ROM_QSTR(MP_QSTR_I2S_WORD_SELECT), MP_ROM_PTR(&pin_GPIO18) }, + + + { MP_ROM_QSTR(MP_QSTR_GP19), MP_ROM_PTR(&pin_GPIO19) }, + { MP_ROM_QSTR(MP_QSTR_GP20), MP_ROM_PTR(&pin_GPIO20) }, + { MP_ROM_QSTR(MP_QSTR_GP21), MP_ROM_PTR(&pin_GPIO21) }, + { MP_ROM_QSTR(MP_QSTR_GP22), MP_ROM_PTR(&pin_GPIO22) }, + { MP_ROM_QSTR(MP_QSTR_GP23), MP_ROM_PTR(&pin_GPIO23) }, + { MP_ROM_QSTR(MP_QSTR_GP24), MP_ROM_PTR(&pin_GPIO24) }, + { MP_ROM_QSTR(MP_QSTR_GP25), MP_ROM_PTR(&pin_GPIO25) }, + + + { MP_ROM_QSTR(MP_QSTR_GP26_A0), MP_ROM_PTR(&pin_GPIO26) }, + { MP_ROM_QSTR(MP_QSTR_GP26), MP_ROM_PTR(&pin_GPIO26) }, + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO26) }, + + + { MP_ROM_QSTR(MP_QSTR_GP27_A1), MP_ROM_PTR(&pin_GPIO27) }, + { MP_ROM_QSTR(MP_QSTR_GP27), MP_ROM_PTR(&pin_GPIO27) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO27) }, + + + { MP_ROM_QSTR(MP_QSTR_GP28_A2), MP_ROM_PTR(&pin_GPIO28) }, + { MP_ROM_QSTR(MP_QSTR_GP28), MP_ROM_PTR(&pin_GPIO28) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO28) }, + + + { MP_ROM_QSTR(MP_QSTR_GP29_A3), MP_ROM_PTR(&pin_GPIO29) }, + { MP_ROM_QSTR(MP_QSTR_GP29), MP_ROM_PTR(&pin_GPIO29) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO29) }, + + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_STEMMA_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, + { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].epaper_display)} +}; + +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); From 77d04589e113c6836cc5298ac907167f6876d3c8 Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Tue, 28 Nov 2023 13:23:11 -0500 Subject: [PATCH 4/9] board.DISPLAY object working but still no output --- .../raspberrypi/boards/dck01/badger-shared.h | 8 + ports/raspberrypi/boards/dck01/board.c | 481 +++++++++++++----- .../raspberrypi/boards/dck01/mpconfigboard.h | 24 +- .../raspberrypi/boards/dck01/mpconfigboard.mk | 7 +- ports/raspberrypi/boards/dck01/pins.c | 80 ++- 5 files changed, 412 insertions(+), 188 deletions(-) create mode 100644 ports/raspberrypi/boards/dck01/badger-shared.h diff --git a/ports/raspberrypi/boards/dck01/badger-shared.h b/ports/raspberrypi/boards/dck01/badger-shared.h new file mode 100644 index 0000000000000..c832616e7d13e --- /dev/null +++ b/ports/raspberrypi/boards/dck01/badger-shared.h @@ -0,0 +1,8 @@ +#ifndef PIMORONI_BADGER2040_SHARED +#define PIMORONI_BADGER2040_SHARED + +#include "shared-bindings/digitalio/DigitalInOut.h" + +extern digitalio_digitalinout_obj_t enable_pin_obj; + +#endif // PIMORONI_BADGER2040_SHARED diff --git a/ports/raspberrypi/boards/dck01/board.c b/ports/raspberrypi/boards/dck01/board.c index 1853a710426b0..51ba0e8e59f03 100644 --- a/ports/raspberrypi/boards/dck01/board.c +++ b/ports/raspberrypi/boards/dck01/board.c @@ -24,189 +24,418 @@ * THE SOFTWARE. */ -// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. - - #include "supervisor/board.h" -#include "supervisor/shared/board.h" + #include "mpconfigboard.h" -#include "shared-bindings/microcontroller/Pin.h" #include "shared-bindings/busio/SPI.h" #include "shared-bindings/displayio/FourWire.h" -// #include "shared-bindings/time/__init__.h" +#include "shared-bindings/microcontroller/Pin.h" #include "shared-module/displayio/__init__.h" -// #include "shared-module/displayio/mipi_constants.h" +#include "supervisor/shared/board.h" +// #include "badger-shared.h" + +// digitalio_digitalinout_obj_t enable_pin_obj; +#if 0 +#define DELAY 0x80 + +enum reg { + PSR = 0x00, + PWR = 0x01, + POF = 0x02, + PFS = 0x03, + PON = 0x04, + PMES = 0x05, + BTST = 0x06, + DSLP = 0x07, + DTM1 = 0x10, + DSP = 0x11, + DRF = 0x12, + DTM2 = 0x13, + LUT_VCOM = 0x20, + LUT_WW = 0x21, + LUT_BW = 0x22, + LUT_WB = 0x23, + LUT_BB = 0x24, + PLL = 0x30, + TSC = 0x40, + TSE = 0x41, + TSR = 0x43, + TSW = 0x42, + CDI = 0x50, + LPD = 0x51, + TCON = 0x60, + TRES = 0x61, + REV = 0x70, + FLG = 0x71, + AMV = 0x80, + VV = 0x81, + VDCS = 0x82, + PTL = 0x90, + PTIN = 0x91, + PTOU = 0x92, + PGM = 0xa0, + APG = 0xa1, + ROTP = 0xa2, + CCSET = 0xe0, + PWS = 0xe3, + TSSET = 0xe5 +}; + +enum PSR_FLAGS { + RES_96x230 = 0b00000000, + RES_96x252 = 0b01000000, + RES_128x296 = 0b10000000, + RES_160x296 = 0b11000000, + + LUT_OTP = 0b00000000, + LUT_REG = 0b00100000, + + FORMAT_BWR = 0b00000000, + FORMAT_BW = 0b00010000, + + SCAN_DOWN = 0b00000000, + SCAN_UP = 0b00001000, -displayio_fourwire_obj_t board_display_obj; + SHIFT_LEFT = 0b00000000, + SHIFT_RIGHT = 0b00000100, -#define HEIGHT 200 -#define WIDTH 200 + BOOSTER_OFF = 0b00000000, + BOOSTER_ON = 0b00000010, + + RESET_SOFT = 0b00000000, + RESET_NONE = 0b00000001 +}; + +enum PWR_FLAGS_1 { + VDS_EXTERNAL = 0b00000000, + VDS_INTERNAL = 0b00000010, + + VDG_EXTERNAL = 0b00000000, + VDG_INTERNAL = 0b00000001 +}; + +enum PWR_FLAGS_2 { + VCOM_VD = 0b00000000, + VCOM_VG = 0b00000100, + + VGHL_16V = 0b00000000, + VGHL_15V = 0b00000001, + VGHL_14V = 0b00000010, + VGHL_13V = 0b00000011 +}; + +enum BOOSTER_FLAGS { + START_10MS = 0b00000000, + START_20MS = 0b01000000, + START_30MS = 0b10000000, + START_40MS = 0b11000000, + + STRENGTH_1 = 0b00000000, + STRENGTH_2 = 0b00001000, + STRENGTH_3 = 0b00010000, + STRENGTH_4 = 0b00011000, + STRENGTH_5 = 0b00100000, + STRENGTH_6 = 0b00101000, + STRENGTH_7 = 0b00110000, + STRENGTH_8 = 0b00111000, + + OFF_0_27US = 0b00000000, + OFF_0_34US = 0b00000001, + OFF_0_40US = 0b00000010, + OFF_0_54US = 0b00000011, + OFF_0_80US = 0b00000100, + OFF_1_54US = 0b00000101, + OFF_3_34US = 0b00000110, + OFF_6_58US = 0b00000111 +}; + +enum PFS_FLAGS { + FRAMES_1 = 0b00000000, + FRAMES_2 = 0b00010000, + FRAMES_3 = 0b00100000, + FRAMES_4 = 0b00110000 +}; -#define DELAY 0x80 +enum TSE_FLAGS { + TEMP_INTERNAL = 0b00000000, + TEMP_EXTERNAL = 0b10000000, + + OFFSET_0 = 0b00000000, + OFFSET_1 = 0b00000001, + OFFSET_2 = 0b00000010, + OFFSET_3 = 0b00000011, + OFFSET_4 = 0b00000100, + OFFSET_5 = 0b00000101, + OFFSET_6 = 0b00000110, + OFFSET_7 = 0b00000111, + + OFFSET_MIN_8 = 0b00001000, + OFFSET_MIN_7 = 0b00001001, + OFFSET_MIN_6 = 0b00001010, + OFFSET_MIN_5 = 0b00001011, + OFFSET_MIN_4 = 0b00001100, + OFFSET_MIN_3 = 0b00001101, + OFFSET_MIN_2 = 0b00001110, + OFFSET_MIN_1 = 0b00001111 +}; + +enum PLL_FLAGS { + // other frequency options exist but there doesn't seem to be much + // point in including them - this is a fair range of options... + HZ_29 = 0b00111111, + HZ_33 = 0b00111110, + HZ_40 = 0b00111101, + HZ_50 = 0b00111100, + HZ_67 = 0b00111011, + HZ_100 = 0b00111010, + HZ_200 = 0b00111001 +}; + +// This is an UC8151 control chip. The display is a 2.9" grayscale EInk. +const uint8_t display_start_sequence[] = { + PWR, 5, VDS_INTERNAL | VDG_INTERNAL, VCOM_VD | VGHL_16V, 0b101011, 0b101011, 0b101011, // power setting + PON, DELAY, 200, // power on and wait 200 ms + BTST, 3, (START_10MS | STRENGTH_3 | OFF_6_58US), (START_10MS | STRENGTH_3 | OFF_6_58US), (START_10MS | STRENGTH_3 | OFF_6_58US), + PSR, 1, (RES_128x296 | LUT_REG | FORMAT_BW | SCAN_UP | SHIFT_RIGHT | BOOSTER_ON | RESET_NONE), + PFS, 1, FRAMES_1, + TSE, 1, TEMP_INTERNAL | OFFSET_0, + TCON, 1, 0x22, // tcon setting + CDI, 1, 0b01001100, // vcom and data interval + PLL, 1, HZ_100, // PLL set to 100 Hz + + // Look up tables for voltage sequence for pixel transition + // Common voltage + LUT_VCOM, 44, + 0x00, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x04, + 0x00, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, + + // White to white + LUT_WW, 42, + 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, + 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // Black to white + LUT_BW, 42, + 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, + 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // White to black + LUT_WB, 42, + 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, + 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // Black to black + LUT_BB, 42, + 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, + 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +const uint8_t display_stop_sequence[] = { + POF, 0x00 // Power off +}; + +const uint8_t refresh_sequence[] = { + DRF, 0x00 +}; + +#endif + +#define HEIGHT 200 +#define WIDTH 200 + +#define DELAY 0x80 #define EPD_RAM_BW 0x10 #define EPD_RAM_RED 0x13 #define BUSY_WAIT 500 // These commands are the combination of SSD1608 and SSD1681 and not all commands are supported for each controller -#define SSD_DRIVER_CONTROL 0x01 -#define SSD_GATE_VOLTAGE 0x03 -#define SSD_SOURCE_VOLTAGE 0x04 -#define SSD_DISPLAY_CONTROL 0x07 -#define SSD_PROGOTP_INITIAL 0x08 -#define SSD_PROGREG_INITIAL 0x09 -#define SSD_READREG_INITIAL 0x0A -#define SSD_NON_OVERLAP 0x0B -#define SSD_BOOST_SOFT_START 0x0C -#define SSD_DEEP_SLEEP 0x10 -#define SSD_DATA_MODE 0x11 -#define SSD_SW_RESET 0x12 -#define SSD1681_TEMP_CONTROL 0x18 -#define SSD1608_TEMP_CONTROL 0x1C -#define SSD_TEMP_WRITE 0x1A -#define SSD_TEMP_READ 0x1B -#define SSD_MASTER_ACTIVATE 0x20 -#define SSD_DISP_CTRL1 0x21 -#define SSD_DISP_CTRL2 0x22 -#define SSD_WRITE_RAM1 0x24 -#define SSD_READ_RAM1 0x24 -#define SSD_WRITE_RAM2 0x26 -#define SSD_READ_RAM2 0x24 -#define SSD_WRITE_VCOM 0x2C -#define SSD_READ_OTP 0x2D -#define SSD_READ_STATUS 0x2F -#define SSD_WRITE_LUT 0x32 -#define SSD_WRITE_DUMMY 0x3A -#define SSD1608_WRITE_GATELINE 0x3B -#define SSD_WRITE_BORDER 0x3C -#define SSD_SET_RAMXPOS 0x44 -#define SSD_SET_RAMYPOS 0x45 -#define SSD_SET_RAMXCOUNT 0x4E -#define SSD_SET_RAMYCOUNT 0x4F -#define SSD_NOP 0xFF - - -#if 1 // SSD1608 - -#define SSD_TEMP_CONTROL SSD1608_TEMP_CONTROL +#define SSD_DRIVER_CONTROL 0x01 +#define SSD_GATE_VOLTAGE 0x03 +#define SSD_SOURCE_VOLTAGE 0x04 +#define SSD_DISPLAY_CONTROL 0x07 +#define SSD_PROGOTP_INITIAL 0x08 +#define SSD_PROGREG_INITIAL 0x09 +#define SSD_READREG_INITIAL 0x0A +#define SSD_NON_OVERLAP 0x0B +#define SSD_BOOST_SOFT_START 0x0C +#define SSD_DEEP_SLEEP 0x10 +#define SSD_DATA_MODE 0x11 +#define SSD_SW_RESET 0x12 +#define SSD1681_TEMP_CONTROL 0x18 +#define SSD1608_TEMP_CONTROL 0x1C +#define SSD_TEMP_WRITE 0x1A +#define SSD_TEMP_READ 0x1B +#define SSD_MASTER_ACTIVATE 0x20 +#define SSD_DISP_CTRL1 0x21 +#define SSD_DISP_CTRL2 0x22 +#define SSD_WRITE_RAM1 0x24 +#define SSD_READ_RAM1 0x24 +#define SSD_WRITE_RAM2 0x26 +#define SSD_READ_RAM2 0x24 +#define SSD_WRITE_VCOM 0x2C +#define SSD_READ_OTP 0x2D +#define SSD_READ_STATUS 0x2F +#define SSD_WRITE_LUT 0x32 +#define SSD_WRITE_DUMMY 0x3A +#define SSD1608_WRITE_GATELINE 0x3B +#define SSD_WRITE_BORDER 0x3C +#define SSD_SET_RAMXPOS 0x44 +#define SSD_SET_RAMYPOS 0x45 +#define SSD_SET_RAMXCOUNT 0x4E +#define SSD_SET_RAMYCOUNT 0x4F +#define SSD_NOP 0xFF + +#if 1 // SSD1608 + +#define SSD_TEMP_CONTROL SSD1608_TEMP_CONTROL const uint8_t _start_sequence[] = { - SSD_SW_RESET, 0, // soft reset - SSD_NOP, 20, // busy wait 20ms - SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00, // set display size - SSD_WRITE_DUMMY, 1, 0x1b, // Set dummy line period - SSD1608_WRITE_GATELINE, 1, 0x0b, // Set gate line width - SSD_DATA_MODE, 1, 0x03, // Data entry sequence - SSD_SET_RAMXPOS, 1, 0x00, - SSD_SET_RAMYPOS, 2, 0x00, 0x00, - SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage - SSD_WRITE_LUT, 30, 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, 0x69, 0x59, 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT - SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes - SSD_NOP, 20, // busy wait + SSD_SW_RESET, 0, // soft reset + SSD_NOP, 500, // busy wait 500ms + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00, // set display size + SSD_WRITE_DUMMY, 1, 0x1b, // Set dummy line period + SSD1608_WRITE_GATELINE, 1, 0x0b, // Set gate line width + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + // SSD_SET_RAMXPOS, 1, 0x00, + // SSD_SET_RAMYPOS, 2, 0x00, 0x00, + SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage + SSD_WRITE_LUT, 30, 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, + 0x69, 0x59, 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 0x00, 0x00, + 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT + SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes + // SSD_NOP, 20, // busy wait }; const uint8_t _stop_sequence[] = { - SSD_DEEP_SLEEP, 1, 0x01 // Enter deep sleep + SSD_DEEP_SLEEP, 1, 0x01 // Enter deep sleep }; const uint8_t _refresh_sequence[] = { - SSD_SW_RESET, 0, // soft reset + 0x20, + 0, }; -#else // SD1681 +#else // SD1681 -#define SSD_TEMP_CONTROL SSD1681_TEMP_CONTROL +#define SSD_TEMP_CONTROL SSD1681_TEMP_CONTROL const uint8_t _start_sequence[] = { - SSD_SW_RESET,, 0x80, 20, // soft reset and wait 20ms - SSD_DATA_MODE, 1, 0x03, // Data entry sequence - SSD_SET_RAMXPOS, 1, 0x00, - SSD_SET_RAMYPOS, 2, 0x00, 0x00, - SSD_WRITE_BORDER, 1, 0x05 // border color - SSD_TEMP_CONTROL, 1, 0x80, // Temp control - SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00 // set display size - SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes + SSD_SW_RESET, , 0x80, 20, // soft reset and wait 20ms + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + SSD_SET_RAMXPOS, 1, 0x00, + SSD_SET_RAMYPOS, 2, 0x00, 0x00, + SSD_WRITE_BORDER, 1, 0x05 // border color + SSD_TEMP_CONTROL, + 1, 0x80, // Temp control + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00 // set display size + SSD_DISP_CTRL2, + 1, 0xc7, // Set DISP only full refreshes }; const uint8_t _stop_sequence[] = { - SSD_DEEP_SLEEP, 0x81, 1, 0x64 // Enter deep sleep + SSD_DEEP_SLEEP, 0x81, 1, 0x64 // Enter deep sleep }; const uint8_t _refresh_sequence[] = { - SSD_SW_RESET, 0, // soft reset + SSD_SW_RESET, 0, // soft reset }; -#endif // EPD choice - +#endif // EPD choice void board_init(void) { + // Drive the EN_3V3 pin high so the board stays awake on battery power + // enable_pin_obj.base.type = &digitalio_digitalinout_type; + // common_hal_digitalio_digitalinout_construct(&enable_pin_obj, &pin_GPIO10); + // common_hal_digitalio_digitalinout_switch_to_output(&enable_pin_obj, true, DRIVE_MODE_PUSH_PULL); + // Never reset + // common_hal_digitalio_digitalinout_never_reset(&enable_pin_obj); + + // Set up the SPI object used to control the display displayio_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus; busio_spi_obj_t *spi = &bus->inline_bus; - - common_hal_busio_spi_construct(spi, DEFAULT_SPI_BUS_SCK, DEFAULT_SPI_BUS_MOSI, NULL, false); + common_hal_busio_spi_construct(spi, &pin_GPIO14, &pin_GPIO15, NULL, false); common_hal_busio_spi_never_reset(spi); // Set up the DisplayIO pin object bus->base.type = &displayio_fourwire_type; - - common_hal_displayio_fourwire_construct( - bus, + common_hal_displayio_fourwire_construct(bus, spi, - DEFAULT_SPI_BUS_DC, // EPD_DC Command or data - DEFAULT_SPI_BUS_CS, // EPD_CS Chip select - DEFAULT_SPI_BUS_RESET, // EPD_RST Reset - 1200000, // Baudrate - 0, // Polarity - 0); // Phase + &pin_GPIO11, // EPD_DC Command or data + &pin_GPIO13, // EPD_CS Chip select + &pin_GPIO10, // EPD_RST Reset + 1200000, // Baudrate + 0, // Polarity + 0); // Phase // Set up the DisplayIO epaper object displayio_epaperdisplay_obj_t *display = &allocate_display()->epaper_display; display->base.type = &displayio_epaperdisplay_type; - common_hal_displayio_epaperdisplay_construct( display, bus, - _start_sequence, - sizeof(_start_sequence), - 0, // start up time - _stop_sequence, - sizeof(_stop_sequence), - WIDTH, // width - HEIGHT, // height - WIDTH, // RAM width - HEIGHT, // RAM height - 0, // colstart - 0, // rowstart - 0, // rotation - NO_COMMAND, // set_column_window_command - NO_COMMAND, // set_row_window_command - NO_COMMAND, // set_current_column_command - NO_COMMAND, // set_current_row_command - 0x13, // write_black_ram_command - false, // black_bits_inverted - NO_COMMAND, // write_color_ram_command (can add this for grayscale eventually) - false, // color_bits_inverted - 0x000000, // highlight_color - _refresh_sequence, // refresh_display_sequence - sizeof(_refresh_sequence), - 45, // refresh_time (seconds) - DEFAULT_SPI_BUS_BUSY, // busy_pin - false, // busy_state - 5, // seconds_per_frame (minimum and Adafruit recommends 180) - false, // chip_select (don't always toggle chip select) - false, // grayscale - false, // acep - false, // two_byte_sequence_length - false // address_little_endian - ); + _start_sequence, sizeof(_start_sequence), + 0, // start up time + _stop_sequence, sizeof(_stop_sequence), + 200, // width + 200, // height + 200, // ram_width + 200, // ram_height + 0, // colstart + 0, // rowstart + 0, // rotation + 0x44, // set_column_window_command + 0x45, // set_row_window_command + 0x4E, // set_current_column_command + 0x4F, // set_current_row_command + 0x24, // write_black_ram_command + false, // black_bits_inverted + NO_COMMAND, // write_color_ram_command + false, // color_bits_inverted + 0x000000, // highlight_color (change this to RED when we have a tri-color display) + _refresh_sequence, sizeof(_refresh_sequence), // refresh_display_command + 1.0, // refresh_time + &pin_GPIO9, // busy_pin + false, // busy_state + 5.0, // seconds_per_frame (does not seem the user can change this) + false, // always_toggle_chip_select + false, // grayscale + false, // acep + false, // two_byte_sequence_length + false); // address_little_endian } - void board_deinit(void) { displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; if (display->base.type == &displayio_epaperdisplay_type) { while (common_hal_displayio_epaperdisplay_get_busy(display)) { - RUN_BACKGROUND_TASKS; + // RUN_BACKGROUND_TASKS; } } common_hal_displayio_release_displays(); diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.h b/ports/raspberrypi/boards/dck01/mpconfigboard.h index 5279961a84e2c..ac90518dcd188 100644 --- a/ports/raspberrypi/boards/dck01/mpconfigboard.h +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.h @@ -1,19 +1,15 @@ -#define MICROPY_HW_BOARD_NAME "RP2040 DCK01" +#define MICROPY_HW_BOARD_NAME "DCK02" #define MICROPY_HW_MCU_NAME "rp2040" -#define MICROPY_HW_LED_STATUS (&pin_GPIO4) -#define MICROPY_HW_NEOPIXEL (&pin_GPIO5) +// Status LED +#define MICROPY_HW_LED_STATUS (&pin_GPIO4) -#define DEFAULT_I2C_BUS_SCL (&pin_GPIO3) -#define DEFAULT_I2C_BUS_SDA (&pin_GPIO2) +#define DEFAULT_UART_BUS_TX (&pin_GPIO0) +#define DEFAULT_UART_BUS_RX (&pin_GPIO1) -#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO9) -#define DEFAULT_SPI_BUS_RESET (&pin_GPIO10) -#define DEFAULT_SPI_BUS_DC (&pin_GPIO11) -#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) -#define DEFAULT_SPI_BUS_CS (&pin_GPIO13) -#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) -#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO2) +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO3) -#define DEFAULT_UART_BUS_RX (&pin_GPIO1) -#define DEFAULT_UART_BUS_TX (&pin_GPIO0) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.mk b/ports/raspberrypi/boards/dck01/mpconfigboard.mk index 268b452d28fe1..a3b34248c45d9 100644 --- a/ports/raspberrypi/boards/dck01/mpconfigboard.mk +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.mk @@ -1,6 +1,6 @@ USB_VID = 0x1209 USB_PID = 0xA182 -USB_PRODUCT = "RP2040 DCK01" +USB_PRODUCT = "RP2040 DCK02" USB_MANUFACTURER = "Bradán Lane STUDIO" CHIP_VARIANT = RP2040 CHIP_FAMILY = rp2 @@ -8,8 +8,3 @@ CHIP_FAMILY = rp2 EXTERNAL_FLASH_DEVICES = "GD25Q64C" CIRCUITPY__EVE = 1 - -FROZEN_MPY_DIRS += $(TOP)/ports/raspberrypi/boards/dck01 -FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_HID -FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel -FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Register diff --git a/ports/raspberrypi/boards/dck01/pins.c b/ports/raspberrypi/boards/dck01/pins.c index c811477ecf0ad..f56cc8e0d4024 100644 --- a/ports/raspberrypi/boards/dck01/pins.c +++ b/ports/raspberrypi/boards/dck01/pins.c @@ -1,62 +1,61 @@ #include "shared-bindings/board/__init__.h" -#include "supervisor/board.h" -#include "shared-module/displayio/__init__.h" +#include "shared-module/displayio/__init__.h" +#include "badger-shared.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS - { MP_ROM_QSTR(MP_QSTR_GP0), MP_ROM_PTR(&pin_GPIO0) }, { MP_ROM_QSTR(MP_QSTR_GP1), MP_ROM_PTR(&pin_GPIO1) }, - - { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO0) }, - { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO1) }, - + // GPIO0 and GPIO1 are also the UART + { MP_ROM_QSTR(MP_QSTR_UART_TX), MP_ROM_PTR(&pin_GPIO0) }, + { MP_ROM_QSTR(MP_QSTR_UART_RX), MP_ROM_PTR(&pin_GPIO1) }, { MP_ROM_QSTR(MP_QSTR_GP2), MP_ROM_PTR(&pin_GPIO2) }, { MP_ROM_QSTR(MP_QSTR_GP3), MP_ROM_PTR(&pin_GPIO3) }, - - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO2) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO3) }, - + // GPIO2 and GPIO3 are also the I2C + { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO2) }, + { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO3) }, { MP_ROM_QSTR(MP_QSTR_GP4), MP_ROM_PTR(&pin_GPIO4) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) }, - + // GPIO4 is also the LED + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO4) }, { MP_ROM_QSTR(MP_QSTR_GP5), MP_ROM_PTR(&pin_GPIO5) }, + // GPIO5 is also the NEOPIXEL { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO5) }, - { MP_ROM_QSTR(MP_QSTR_GP6), MP_ROM_PTR(&pin_GPIO6) }, + // GPIO6 is also the speaker (PWM) { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPIO6) }, - { MP_ROM_QSTR(MP_QSTR_GP7), MP_ROM_PTR(&pin_GPIO7) }, { MP_ROM_QSTR(MP_QSTR_GP8), MP_ROM_PTR(&pin_GPIO8) }, + { MP_ROM_QSTR(MP_QSTR_GP9), MP_ROM_PTR(&pin_GPIO9) }, { MP_ROM_QSTR(MP_QSTR_GP10), MP_ROM_PTR(&pin_GPIO10) }, { MP_ROM_QSTR(MP_QSTR_GP11), MP_ROM_PTR(&pin_GPIO11) }, - - { MP_ROM_QSTR(MP_QSTR_GP12), MP_ROM_PTR(&pin_GPIO12) }, { MP_ROM_QSTR(MP_QSTR_GP13), MP_ROM_PTR(&pin_GPIO13) }, { MP_ROM_QSTR(MP_QSTR_GP14), MP_ROM_PTR(&pin_GPIO14) }, { MP_ROM_QSTR(MP_QSTR_GP15), MP_ROM_PTR(&pin_GPIO15) }, - - { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO12) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO14) }, - { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO15) }, - + // GPIO9 thru GPIO15 are the SPI for the ePaper display + { MP_ROM_QSTR(MP_QSTR_SPI_BUSY), MP_ROM_PTR(&pin_GPIO9) }, + { MP_ROM_QSTR(MP_QSTR_SPI_RESET), MP_ROM_PTR(&pin_GPIO10) }, + { MP_ROM_QSTR(MP_QSTR_SPI_DC), MP_ROM_PTR(&pin_GPIO11) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MISO), MP_ROM_PTR(&pin_GPIO12) }, + { MP_ROM_QSTR(MP_QSTR_SPI_CS), MP_ROM_PTR(&pin_GPIO13) }, + { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_GPIO14) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(&pin_GPIO15) }, { MP_ROM_QSTR(MP_QSTR_GP16), MP_ROM_PTR(&pin_GPIO16) }, { MP_ROM_QSTR(MP_QSTR_GP17), MP_ROM_PTR(&pin_GPIO17) }, { MP_ROM_QSTR(MP_QSTR_GP18), MP_ROM_PTR(&pin_GPIO18) }, + // GPIO16 thru GPIO18 are also the I2S audio { MP_ROM_QSTR(MP_QSTR_I2S_DATA), MP_ROM_PTR(&pin_GPIO16) }, - { MP_ROM_QSTR(MP_QSTR_I2S_BIT_CLOCK), MP_ROM_PTR(&pin_GPIO17) }, - { MP_ROM_QSTR(MP_QSTR_I2S_WORD_SELECT), MP_ROM_PTR(&pin_GPIO18) }, - + { MP_ROM_QSTR(MP_QSTR_I2S_BCK), MP_ROM_PTR(&pin_GPIO17) }, + { MP_ROM_QSTR(MP_QSTR_I2S_LRCK), MP_ROM_PTR(&pin_GPIO18) }, { MP_ROM_QSTR(MP_QSTR_GP19), MP_ROM_PTR(&pin_GPIO19) }, { MP_ROM_QSTR(MP_QSTR_GP20), MP_ROM_PTR(&pin_GPIO20) }, @@ -64,34 +63,31 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP22), MP_ROM_PTR(&pin_GPIO22) }, { MP_ROM_QSTR(MP_QSTR_GP23), MP_ROM_PTR(&pin_GPIO23) }, { MP_ROM_QSTR(MP_QSTR_GP24), MP_ROM_PTR(&pin_GPIO24) }, - { MP_ROM_QSTR(MP_QSTR_GP25), MP_ROM_PTR(&pin_GPIO25) }, + // GPIO19 thru GPIO24 are also the touch pads + { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_GPIO19) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_GPIO20) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_GPIO21) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_GPIO22) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH5), MP_ROM_PTR(&pin_GPIO23) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH6), MP_ROM_PTR(&pin_GPIO24) }, + { MP_ROM_QSTR(MP_QSTR_GP25), MP_ROM_PTR(&pin_GPIO25) }, - { MP_ROM_QSTR(MP_QSTR_GP26_A0), MP_ROM_PTR(&pin_GPIO26) }, { MP_ROM_QSTR(MP_QSTR_GP26), MP_ROM_PTR(&pin_GPIO26) }, - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO26) }, - - - { MP_ROM_QSTR(MP_QSTR_GP27_A1), MP_ROM_PTR(&pin_GPIO27) }, { MP_ROM_QSTR(MP_QSTR_GP27), MP_ROM_PTR(&pin_GPIO27) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO27) }, - - - { MP_ROM_QSTR(MP_QSTR_GP28_A2), MP_ROM_PTR(&pin_GPIO28) }, { MP_ROM_QSTR(MP_QSTR_GP28), MP_ROM_PTR(&pin_GPIO28) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO28) }, - - - { MP_ROM_QSTR(MP_QSTR_GP29_A3), MP_ROM_PTR(&pin_GPIO29) }, { MP_ROM_QSTR(MP_QSTR_GP29), MP_ROM_PTR(&pin_GPIO29) }, + // GPIO26 thru GPIO29 are also the analog pins + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO26) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO27) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO28) }, { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO29) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, - { MP_ROM_QSTR(MP_QSTR_STEMMA_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, - { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].epaper_display)} -}; + { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].epaper_display)}, +}; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); From 3fe94312814da637980341a4596fc69159a900bc Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Tue, 28 Nov 2023 13:41:45 -0500 Subject: [PATCH 5/9] remove temporary code --- .../raspberrypi/boards/dck01/badger-shared.h | 8 - ports/raspberrypi/boards/dck01/board.c | 256 +----------------- ports/raspberrypi/boards/dck01/pins.c | 2 - 3 files changed, 10 insertions(+), 256 deletions(-) delete mode 100644 ports/raspberrypi/boards/dck01/badger-shared.h diff --git a/ports/raspberrypi/boards/dck01/badger-shared.h b/ports/raspberrypi/boards/dck01/badger-shared.h deleted file mode 100644 index c832616e7d13e..0000000000000 --- a/ports/raspberrypi/boards/dck01/badger-shared.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef PIMORONI_BADGER2040_SHARED -#define PIMORONI_BADGER2040_SHARED - -#include "shared-bindings/digitalio/DigitalInOut.h" - -extern digitalio_digitalinout_obj_t enable_pin_obj; - -#endif // PIMORONI_BADGER2040_SHARED diff --git a/ports/raspberrypi/boards/dck01/board.c b/ports/raspberrypi/boards/dck01/board.c index 51ba0e8e59f03..8436bb7f3a5c0 100644 --- a/ports/raspberrypi/boards/dck01/board.c +++ b/ports/raspberrypi/boards/dck01/board.c @@ -32,239 +32,6 @@ #include "shared-bindings/microcontroller/Pin.h" #include "shared-module/displayio/__init__.h" #include "supervisor/shared/board.h" -// #include "badger-shared.h" - -// digitalio_digitalinout_obj_t enable_pin_obj; -#if 0 -#define DELAY 0x80 - -enum reg { - PSR = 0x00, - PWR = 0x01, - POF = 0x02, - PFS = 0x03, - PON = 0x04, - PMES = 0x05, - BTST = 0x06, - DSLP = 0x07, - DTM1 = 0x10, - DSP = 0x11, - DRF = 0x12, - DTM2 = 0x13, - LUT_VCOM = 0x20, - LUT_WW = 0x21, - LUT_BW = 0x22, - LUT_WB = 0x23, - LUT_BB = 0x24, - PLL = 0x30, - TSC = 0x40, - TSE = 0x41, - TSR = 0x43, - TSW = 0x42, - CDI = 0x50, - LPD = 0x51, - TCON = 0x60, - TRES = 0x61, - REV = 0x70, - FLG = 0x71, - AMV = 0x80, - VV = 0x81, - VDCS = 0x82, - PTL = 0x90, - PTIN = 0x91, - PTOU = 0x92, - PGM = 0xa0, - APG = 0xa1, - ROTP = 0xa2, - CCSET = 0xe0, - PWS = 0xe3, - TSSET = 0xe5 -}; - -enum PSR_FLAGS { - RES_96x230 = 0b00000000, - RES_96x252 = 0b01000000, - RES_128x296 = 0b10000000, - RES_160x296 = 0b11000000, - - LUT_OTP = 0b00000000, - LUT_REG = 0b00100000, - - FORMAT_BWR = 0b00000000, - FORMAT_BW = 0b00010000, - - SCAN_DOWN = 0b00000000, - SCAN_UP = 0b00001000, - - SHIFT_LEFT = 0b00000000, - SHIFT_RIGHT = 0b00000100, - - BOOSTER_OFF = 0b00000000, - BOOSTER_ON = 0b00000010, - - RESET_SOFT = 0b00000000, - RESET_NONE = 0b00000001 -}; - -enum PWR_FLAGS_1 { - VDS_EXTERNAL = 0b00000000, - VDS_INTERNAL = 0b00000010, - - VDG_EXTERNAL = 0b00000000, - VDG_INTERNAL = 0b00000001 -}; - -enum PWR_FLAGS_2 { - VCOM_VD = 0b00000000, - VCOM_VG = 0b00000100, - - VGHL_16V = 0b00000000, - VGHL_15V = 0b00000001, - VGHL_14V = 0b00000010, - VGHL_13V = 0b00000011 -}; - -enum BOOSTER_FLAGS { - START_10MS = 0b00000000, - START_20MS = 0b01000000, - START_30MS = 0b10000000, - START_40MS = 0b11000000, - - STRENGTH_1 = 0b00000000, - STRENGTH_2 = 0b00001000, - STRENGTH_3 = 0b00010000, - STRENGTH_4 = 0b00011000, - STRENGTH_5 = 0b00100000, - STRENGTH_6 = 0b00101000, - STRENGTH_7 = 0b00110000, - STRENGTH_8 = 0b00111000, - - OFF_0_27US = 0b00000000, - OFF_0_34US = 0b00000001, - OFF_0_40US = 0b00000010, - OFF_0_54US = 0b00000011, - OFF_0_80US = 0b00000100, - OFF_1_54US = 0b00000101, - OFF_3_34US = 0b00000110, - OFF_6_58US = 0b00000111 -}; - -enum PFS_FLAGS { - FRAMES_1 = 0b00000000, - FRAMES_2 = 0b00010000, - FRAMES_3 = 0b00100000, - FRAMES_4 = 0b00110000 -}; - -enum TSE_FLAGS { - TEMP_INTERNAL = 0b00000000, - TEMP_EXTERNAL = 0b10000000, - - OFFSET_0 = 0b00000000, - OFFSET_1 = 0b00000001, - OFFSET_2 = 0b00000010, - OFFSET_3 = 0b00000011, - OFFSET_4 = 0b00000100, - OFFSET_5 = 0b00000101, - OFFSET_6 = 0b00000110, - OFFSET_7 = 0b00000111, - - OFFSET_MIN_8 = 0b00001000, - OFFSET_MIN_7 = 0b00001001, - OFFSET_MIN_6 = 0b00001010, - OFFSET_MIN_5 = 0b00001011, - OFFSET_MIN_4 = 0b00001100, - OFFSET_MIN_3 = 0b00001101, - OFFSET_MIN_2 = 0b00001110, - OFFSET_MIN_1 = 0b00001111 -}; - -enum PLL_FLAGS { - // other frequency options exist but there doesn't seem to be much - // point in including them - this is a fair range of options... - HZ_29 = 0b00111111, - HZ_33 = 0b00111110, - HZ_40 = 0b00111101, - HZ_50 = 0b00111100, - HZ_67 = 0b00111011, - HZ_100 = 0b00111010, - HZ_200 = 0b00111001 -}; - -// This is an UC8151 control chip. The display is a 2.9" grayscale EInk. -const uint8_t display_start_sequence[] = { - PWR, 5, VDS_INTERNAL | VDG_INTERNAL, VCOM_VD | VGHL_16V, 0b101011, 0b101011, 0b101011, // power setting - PON, DELAY, 200, // power on and wait 200 ms - BTST, 3, (START_10MS | STRENGTH_3 | OFF_6_58US), (START_10MS | STRENGTH_3 | OFF_6_58US), (START_10MS | STRENGTH_3 | OFF_6_58US), - PSR, 1, (RES_128x296 | LUT_REG | FORMAT_BW | SCAN_UP | SHIFT_RIGHT | BOOSTER_ON | RESET_NONE), - PFS, 1, FRAMES_1, - TSE, 1, TEMP_INTERNAL | OFFSET_0, - TCON, 1, 0x22, // tcon setting - CDI, 1, 0b01001100, // vcom and data interval - PLL, 1, HZ_100, // PLL set to 100 Hz - - // Look up tables for voltage sequence for pixel transition - // Common voltage - LUT_VCOM, 44, - 0x00, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x04, - 0x00, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, - - // White to white - LUT_WW, 42, - 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, - 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - // Black to white - LUT_BW, 42, - 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, - 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - // White to black - LUT_WB, 42, - 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, - 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - // Black to black - LUT_BB, 42, - 0xa8, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x60, 0x8c, 0x8c, 0x00, 0x00, 0x04, - 0x54, 0x64, 0x64, 0x37, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -const uint8_t display_stop_sequence[] = { - POF, 0x00 // Power off -}; - -const uint8_t refresh_sequence[] = { - DRF, 0x00 -}; - -#endif #define HEIGHT 200 #define WIDTH 200 @@ -318,19 +85,20 @@ const uint8_t refresh_sequence[] = { const uint8_t _start_sequence[] = { SSD_SW_RESET, 0, // soft reset - SSD_NOP, 500, // busy wait 500ms + SSD_NOP, 200, // busy wait 200ms SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00, // set display size SSD_WRITE_DUMMY, 1, 0x1b, // Set dummy line period SSD1608_WRITE_GATELINE, 1, 0x0b, // Set gate line width SSD_DATA_MODE, 1, 0x03, // Data entry sequence // SSD_SET_RAMXPOS, 1, 0x00, // SSD_SET_RAMYPOS, 2, 0x00, 0x00, - SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage - SSD_WRITE_LUT, 30, 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, + SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage + SSD_WRITE_LUT, 30, + 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, 0x69, 0x59, 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 0x00, 0x00, - 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT - SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes - // SSD_NOP, 20, // busy wait + 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT + SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes + // SSD_NOP, 20, // busy wait }; const uint8_t _stop_sequence[] = { @@ -369,14 +137,9 @@ const uint8_t _refresh_sequence[] = { #endif // EPD choice -void board_init(void) { - // Drive the EN_3V3 pin high so the board stays awake on battery power - // enable_pin_obj.base.type = &digitalio_digitalinout_type; - // common_hal_digitalio_digitalinout_construct(&enable_pin_obj, &pin_GPIO10); - // common_hal_digitalio_digitalinout_switch_to_output(&enable_pin_obj, true, DRIVE_MODE_PUSH_PULL); - // Never reset - // common_hal_digitalio_digitalinout_never_reset(&enable_pin_obj); + +void board_init(void) { // Set up the SPI object used to control the display displayio_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus; busio_spi_obj_t *spi = &bus->inline_bus; @@ -397,6 +160,7 @@ void board_init(void) { // Set up the DisplayIO epaper object displayio_epaperdisplay_obj_t *display = &allocate_display()->epaper_display; display->base.type = &displayio_epaperdisplay_type; + common_hal_displayio_epaperdisplay_construct( display, bus, diff --git a/ports/raspberrypi/boards/dck01/pins.c b/ports/raspberrypi/boards/dck01/pins.c index f56cc8e0d4024..3c89a25384a85 100644 --- a/ports/raspberrypi/boards/dck01/pins.c +++ b/ports/raspberrypi/boards/dck01/pins.c @@ -1,7 +1,5 @@ #include "shared-bindings/board/__init__.h" - #include "shared-module/displayio/__init__.h" -#include "badger-shared.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS From c53e716804a9dfada6762e808f6d846589a20b7a Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Wed, 29 Nov 2023 15:47:19 -0500 Subject: [PATCH 6/9] DCK01 working! --- ports/raspberrypi/boards/dck01/board.c | 135 +++++++----------- .../raspberrypi/boards/dck01/mpconfigboard.h | 75 ++++++++-- .../raspberrypi/boards/dck01/mpconfigboard.mk | 5 +- ports/raspberrypi/boards/dck01/pins.c | 55 +++++++ 4 files changed, 176 insertions(+), 94 deletions(-) diff --git a/ports/raspberrypi/boards/dck01/board.c b/ports/raspberrypi/boards/dck01/board.c index 8436bb7f3a5c0..7aa08593156d7 100644 --- a/ports/raspberrypi/boards/dck01/board.c +++ b/ports/raspberrypi/boards/dck01/board.c @@ -1,9 +1,7 @@ /* - * This file is part of the MicroPython project, http://micropython.org/ - * * The MIT License (MIT) * - * Copyright (c) 2021 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2023 Bradán Lane STUDIO * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +25,7 @@ #include "supervisor/board.h" #include "mpconfigboard.h" + #include "shared-bindings/busio/SPI.h" #include "shared-bindings/displayio/FourWire.h" #include "shared-bindings/microcontroller/Pin.h" @@ -36,11 +35,11 @@ #define HEIGHT 200 #define WIDTH 200 -#define DELAY 0x80 +#define DELAY_FLAG 0x80 #define EPD_RAM_BW 0x10 #define EPD_RAM_RED 0x13 -#define BUSY_WAIT 500 +// #define BUSY_WAIT 500 // These commands are the combination of SSD1608 and SSD1681 and not all commands are supported for each controller #define SSD_DRIVER_CONTROL 0x01 @@ -48,26 +47,34 @@ #define SSD_SOURCE_VOLTAGE 0x04 #define SSD_DISPLAY_CONTROL 0x07 #define SSD_PROGOTP_INITIAL 0x08 -#define SSD_PROGREG_INITIAL 0x09 +#define SSD_WRITEREG_INITIAL 0x09 #define SSD_READREG_INITIAL 0x0A #define SSD_NON_OVERLAP 0x0B #define SSD_BOOST_SOFT_START 0x0C #define SSD_DEEP_SLEEP 0x10 #define SSD_DATA_MODE 0x11 #define SSD_SW_RESET 0x12 +#define SSD_HV_DETECT 0x14 +#define SSD_VCI_DETECT 0x15 #define SSD1681_TEMP_CONTROL 0x18 #define SSD1608_TEMP_CONTROL 0x1C #define SSD_TEMP_WRITE 0x1A #define SSD_TEMP_READ 0x1B +#define SSD_TEMP_EXTERN 0x1C #define SSD_MASTER_ACTIVATE 0x20 #define SSD_DISP_CTRL1 0x21 #define SSD_DISP_CTRL2 0x22 -#define SSD_WRITE_RAM1 0x24 -#define SSD_READ_RAM1 0x24 -#define SSD_WRITE_RAM2 0x26 -#define SSD_READ_RAM2 0x24 -#define SSD_WRITE_VCOM 0x2C +#define SSD_WRITE_RAM_BLK 0x24 +// #define SSD_READ_RAM_BLK 0x25 +#define SSD_WRITE_RAM_RED 0x26 +// #define SSD_READ_RAM_RED 0x27 +#define SSD_VCOM_SENSE 0x28 +// #define SSD_VCOM_DURRATION 0x29 +// #define SSD_PROG_VCOM 0x2A +// #define SSD_CTRL_VCOM 0x2B +// #define SSD_WRITE_VCOM 0x2C #define SSD_READ_OTP 0x2D +#define SSD_READ_ID 0x2E #define SSD_READ_STATUS 0x2F #define SSD_WRITE_LUT 0x32 #define SSD_WRITE_DUMMY 0x3A @@ -79,81 +86,43 @@ #define SSD_SET_RAMYCOUNT 0x4F #define SSD_NOP 0xFF -#if 1 // SSD1608 - -#define SSD_TEMP_CONTROL SSD1608_TEMP_CONTROL - -const uint8_t _start_sequence[] = { - SSD_SW_RESET, 0, // soft reset - SSD_NOP, 200, // busy wait 200ms - SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00, // set display size - SSD_WRITE_DUMMY, 1, 0x1b, // Set dummy line period - SSD1608_WRITE_GATELINE, 1, 0x0b, // Set gate line width - SSD_DATA_MODE, 1, 0x03, // Data entry sequence - // SSD_SET_RAMXPOS, 1, 0x00, - // SSD_SET_RAMYPOS, 2, 0x00, 0x00, - SSD_WRITE_VCOM, 1, 0x70, // Vcom Voltage - SSD_WRITE_LUT, 30, - 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 0x22, 0x22, 0x66, 0x69, - 0x69, 0x59, 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 0x00, 0x00, - 0xf8, 0xb4, 0x13, 0x51, 0x35, 0x51, 0x51, 0x19, 0x01, 0x00, // LUT - SSD_DISP_CTRL2, 1, 0xc7, // Set DISP only full refreshes - // SSD_NOP, 20, // busy wait -}; - -const uint8_t _stop_sequence[] = { - SSD_DEEP_SLEEP, 1, 0x01 // Enter deep sleep -}; - -const uint8_t _refresh_sequence[] = { - 0x20, - 0, -}; - -#else // SD1681 - #define SSD_TEMP_CONTROL SSD1681_TEMP_CONTROL const uint8_t _start_sequence[] = { - SSD_SW_RESET, , 0x80, 20, // soft reset and wait 20ms - SSD_DATA_MODE, 1, 0x03, // Data entry sequence - SSD_SET_RAMXPOS, 1, 0x00, - SSD_SET_RAMYPOS, 2, 0x00, 0x00, - SSD_WRITE_BORDER, 1, 0x05 // border color - SSD_TEMP_CONTROL, - 1, 0x80, // Temp control - SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), ((WIDTH - 1) >> 8), 0x00 // set display size - SSD_DISP_CTRL2, - 1, 0xc7, // Set DISP only full refreshes + SSD_SW_RESET, DELAY_FLAG + 0, 20, // soft reset and wait 20ms + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + SSD_WRITE_BORDER, 1, 0x05, // border color + SSD_TEMP_CONTROL, 1, 0x80, // Temp control + SSD_SET_RAMXCOUNT, 1, 0x00, + SSD_SET_RAMYCOUNT, 2, 0x00, 0x00, + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), (((WIDTH >> 8) - 1) & 0xFF), 0x00, // set display size + SSD_DISP_CTRL2, 1, 0xf7, // Set DISP only full refreshes }; const uint8_t _stop_sequence[] = { - SSD_DEEP_SLEEP, 0x81, 1, 0x64 // Enter deep sleep + SSD_DEEP_SLEEP, DELAY_FLAG + 1, 1, 0x64 // Enter deep sleep }; const uint8_t _refresh_sequence[] = { - SSD_SW_RESET, 0, // soft reset + SSD_MASTER_ACTIVATE, 0, +// SSD_SW_RESET, 0, }; -#endif // EPD choice - - - void board_init(void) { // Set up the SPI object used to control the display displayio_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus; busio_spi_obj_t *spi = &bus->inline_bus; - common_hal_busio_spi_construct(spi, &pin_GPIO14, &pin_GPIO15, NULL, false); + common_hal_busio_spi_construct(spi, DEFAULT_SPI_BUS_SCK, DEFAULT_SPI_BUS_MOSI, NULL, false); common_hal_busio_spi_never_reset(spi); // Set up the DisplayIO pin object bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, - &pin_GPIO11, // EPD_DC Command or data - &pin_GPIO13, // EPD_CS Chip select - &pin_GPIO10, // EPD_RST Reset - 1200000, // Baudrate + DEFAULT_SPI_BUS_DC, // EPD_DC Command or data + DEFAULT_SPI_BUS_CS, // EPD_CS Chip select + DEFAULT_SPI_BUS_RESET, // EPD_RST Reset + 1000000, // Baudrate 0, // Polarity 0); // Phase @@ -165,34 +134,34 @@ void board_init(void) { display, bus, _start_sequence, sizeof(_start_sequence), - 0, // start up time + 1.0, // start up time _stop_sequence, sizeof(_stop_sequence), - 200, // width - 200, // height - 200, // ram_width - 200, // ram_height + WIDTH, // width + HEIGHT, // height + WIDTH, // ram_width + HEIGHT + 0x60, // ram_height RAM is actually only 200 bits high but we use 296 to match the 9 bits 0, // colstart 0, // rowstart 0, // rotation - 0x44, // set_column_window_command - 0x45, // set_row_window_command - 0x4E, // set_current_column_command - 0x4F, // set_current_row_command - 0x24, // write_black_ram_command + SSD_SET_RAMXPOS, // set_column_window_command + SSD_SET_RAMYPOS, // set_row_window_command + SSD_SET_RAMXCOUNT, // set_current_column_command + SSD_SET_RAMYCOUNT, // set_current_row_command + SSD_WRITE_RAM_BLK, // write_black_ram_command false, // black_bits_inverted - NO_COMMAND, // write_color_ram_command + SSD_WRITE_RAM_RED, // write_color_ram_command false, // color_bits_inverted - 0x000000, // highlight_color (change this to RED when we have a tri-color display) + 0xFF0000, // highlight_color (RED for tri-color display) _refresh_sequence, sizeof(_refresh_sequence), // refresh_display_command - 1.0, // refresh_time - &pin_GPIO9, // busy_pin - false, // busy_state - 5.0, // seconds_per_frame (does not seem the user can change this) - false, // always_toggle_chip_select + 15.0, // refresh_time + DEFAULT_SPI_BUS_BUSY, // busy_pin + true, // busy_state + 20.0, // seconds_per_frame (does not seem the user can change this) + true, // always_toggle_chip_select false, // grayscale false, // acep false, // two_byte_sequence_length - false); // address_little_endian + true); // address_little_endian } void board_deinit(void) { diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.h b/ports/raspberrypi/boards/dck01/mpconfigboard.h index ac90518dcd188..a2bef2d7561f1 100644 --- a/ports/raspberrypi/boards/dck01/mpconfigboard.h +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.h @@ -1,15 +1,70 @@ -#define MICROPY_HW_BOARD_NAME "DCK02" +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Bradán Lane STUDIO + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#define MICROPY_HW_BOARD_NAME "DCK01" #define MICROPY_HW_MCU_NAME "rp2040" -// Status LED -#define MICROPY_HW_LED_STATUS (&pin_GPIO4) +#define DCK01_PROTOTYPE // only needed until the production PCBs are available + + + + +#ifdef DCK01_PROTOTYPE + +// #define MICROPY_HW_LED_STATUS (&pin_GPIO4) + +#define DEFAULT_UART_BUS_TX (&pin_GPIO0) +#define DEFAULT_UART_BUS_RX (&pin_GPIO1) + +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO8) +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO9) + +#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO21) +#define DEFAULT_SPI_BUS_RESET (&pin_GPIO20) +#define DEFAULT_SPI_BUS_DC (&pin_GPIO16) +// #define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) +#define DEFAULT_SPI_BUS_CS (&pin_GPIO17) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO18) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO19) + +#else + +#define MICROPY_HW_LED_STATUS (&pin_GPIO4) + +#define DEFAULT_UART_BUS_TX (&pin_GPIO0) +#define DEFAULT_UART_BUS_RX (&pin_GPIO1) -#define DEFAULT_UART_BUS_TX (&pin_GPIO0) -#define DEFAULT_UART_BUS_RX (&pin_GPIO1) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO8) +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO9) -#define DEFAULT_I2C_BUS_SDA (&pin_GPIO2) -#define DEFAULT_I2C_BUS_SCL (&pin_GPIO3) +#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO9) +#define DEFAULT_SPI_BUS_RESET (&pin_GPIO10) +#define DEFAULT_SPI_BUS_DC (&pin_GPIO11) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) +#define DEFAULT_SPI_BUS_CS (&pin_GPIO13) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) -#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) -#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) -#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) +#endif diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.mk b/ports/raspberrypi/boards/dck01/mpconfigboard.mk index a3b34248c45d9..e2a22aa0e2a19 100644 --- a/ports/raspberrypi/boards/dck01/mpconfigboard.mk +++ b/ports/raspberrypi/boards/dck01/mpconfigboard.mk @@ -1,6 +1,6 @@ USB_VID = 0x1209 USB_PID = 0xA182 -USB_PRODUCT = "RP2040 DCK02" +USB_PRODUCT = "RP2040 DCK01" USB_MANUFACTURER = "Bradán Lane STUDIO" CHIP_VARIANT = RP2040 CHIP_FAMILY = rp2 @@ -8,3 +8,6 @@ CHIP_FAMILY = rp2 EXTERNAL_FLASH_DEVICES = "GD25Q64C" CIRCUITPY__EVE = 1 + +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Display_Text diff --git a/ports/raspberrypi/boards/dck01/pins.c b/ports/raspberrypi/boards/dck01/pins.c index 3c89a25384a85..8d0dbad8c57c6 100644 --- a/ports/raspberrypi/boards/dck01/pins.c +++ b/ports/raspberrypi/boards/dck01/pins.c @@ -1,3 +1,29 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Bradán Lane STUDIO + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mpconfigboard.h" + #include "shared-bindings/board/__init__.h" #include "shared-module/displayio/__init__.h" @@ -13,20 +39,37 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP2), MP_ROM_PTR(&pin_GPIO2) }, { MP_ROM_QSTR(MP_QSTR_GP3), MP_ROM_PTR(&pin_GPIO3) }, // GPIO2 and GPIO3 are also the I2C + #ifdef DCK01_PROTOTYPE + { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO8) }, + { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO9) }, + #else { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO2) }, { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO3) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP4), MP_ROM_PTR(&pin_GPIO4) }, // GPIO4 is also the LED + #ifdef DCK01_PROTOTYPE + // not defined on prototype + #else { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO4) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP5), MP_ROM_PTR(&pin_GPIO5) }, // GPIO5 is also the NEOPIXEL + #ifdef DCK01_PROTOTYPE + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO10) }, + #else { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO5) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP6), MP_ROM_PTR(&pin_GPIO6) }, // GPIO6 is also the speaker (PWM) + #ifdef DCK01_PROTOTYPE { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPIO6) }, + #else + { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPI11) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP7), MP_ROM_PTR(&pin_GPIO7) }, { MP_ROM_QSTR(MP_QSTR_GP8), MP_ROM_PTR(&pin_GPIO8) }, @@ -39,6 +82,9 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP14), MP_ROM_PTR(&pin_GPIO14) }, { MP_ROM_QSTR(MP_QSTR_GP15), MP_ROM_PTR(&pin_GPIO15) }, // GPIO9 thru GPIO15 are the SPI for the ePaper display + #ifdef DCK01_PROTOTYPE + // not defined on prototype + #else { MP_ROM_QSTR(MP_QSTR_SPI_BUSY), MP_ROM_PTR(&pin_GPIO9) }, { MP_ROM_QSTR(MP_QSTR_SPI_RESET), MP_ROM_PTR(&pin_GPIO10) }, { MP_ROM_QSTR(MP_QSTR_SPI_DC), MP_ROM_PTR(&pin_GPIO11) }, @@ -46,14 +92,19 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_SPI_CS), MP_ROM_PTR(&pin_GPIO13) }, { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_GPIO14) }, { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(&pin_GPIO15) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP16), MP_ROM_PTR(&pin_GPIO16) }, { MP_ROM_QSTR(MP_QSTR_GP17), MP_ROM_PTR(&pin_GPIO17) }, { MP_ROM_QSTR(MP_QSTR_GP18), MP_ROM_PTR(&pin_GPIO18) }, // GPIO16 thru GPIO18 are also the I2S audio + #ifdef DCK01_PROTOTYPE + // not defined on prototype + #else { MP_ROM_QSTR(MP_QSTR_I2S_DATA), MP_ROM_PTR(&pin_GPIO16) }, { MP_ROM_QSTR(MP_QSTR_I2S_BCK), MP_ROM_PTR(&pin_GPIO17) }, { MP_ROM_QSTR(MP_QSTR_I2S_LRCK), MP_ROM_PTR(&pin_GPIO18) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP19), MP_ROM_PTR(&pin_GPIO19) }, { MP_ROM_QSTR(MP_QSTR_GP20), MP_ROM_PTR(&pin_GPIO20) }, @@ -62,12 +113,16 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP23), MP_ROM_PTR(&pin_GPIO23) }, { MP_ROM_QSTR(MP_QSTR_GP24), MP_ROM_PTR(&pin_GPIO24) }, // GPIO19 thru GPIO24 are also the touch pads + #ifdef DCK01_PROTOTYPE + // not defined on prototype + #else { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_GPIO19) }, { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_GPIO20) }, { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_GPIO21) }, { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_GPIO22) }, { MP_ROM_QSTR(MP_QSTR_TOUCH5), MP_ROM_PTR(&pin_GPIO23) }, { MP_ROM_QSTR(MP_QSTR_TOUCH6), MP_ROM_PTR(&pin_GPIO24) }, + #endif { MP_ROM_QSTR(MP_QSTR_GP25), MP_ROM_PTR(&pin_GPIO25) }, From e84c90b231e90f1335c147df209727b09b522082 Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Wed, 29 Nov 2023 16:07:36 -0500 Subject: [PATCH 7/9] change folder name to include bradanlane --- ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/board.c | 0 .../boards/{dck01 => bradanlane_dck01}/mpconfigboard.h | 0 .../boards/{dck01 => bradanlane_dck01}/mpconfigboard.mk | 0 .../boards/{dck01 => bradanlane_dck01}/pico-sdk-configboard.h | 0 ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/pins.c | 0 5 files changed, 0 insertions(+), 0 deletions(-) rename ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/board.c (100%) rename ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/mpconfigboard.h (100%) rename ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/mpconfigboard.mk (100%) rename ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/pico-sdk-configboard.h (100%) rename ports/raspberrypi/boards/{dck01 => bradanlane_dck01}/pins.c (100%) diff --git a/ports/raspberrypi/boards/dck01/board.c b/ports/raspberrypi/boards/bradanlane_dck01/board.c similarity index 100% rename from ports/raspberrypi/boards/dck01/board.c rename to ports/raspberrypi/boards/bradanlane_dck01/board.c diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.h b/ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.h similarity index 100% rename from ports/raspberrypi/boards/dck01/mpconfigboard.h rename to ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.h diff --git a/ports/raspberrypi/boards/dck01/mpconfigboard.mk b/ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.mk similarity index 100% rename from ports/raspberrypi/boards/dck01/mpconfigboard.mk rename to ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.mk diff --git a/ports/raspberrypi/boards/dck01/pico-sdk-configboard.h b/ports/raspberrypi/boards/bradanlane_dck01/pico-sdk-configboard.h similarity index 100% rename from ports/raspberrypi/boards/dck01/pico-sdk-configboard.h rename to ports/raspberrypi/boards/bradanlane_dck01/pico-sdk-configboard.h diff --git a/ports/raspberrypi/boards/dck01/pins.c b/ports/raspberrypi/boards/bradanlane_dck01/pins.c similarity index 100% rename from ports/raspberrypi/boards/dck01/pins.c rename to ports/raspberrypi/boards/bradanlane_dck01/pins.c From 25676f0a7d5338fe339f8e70deafe03355c57ac3 Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Wed, 29 Nov 2023 16:09:42 -0500 Subject: [PATCH 8/9] changed folder name to include rp2040 --- .../boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/board.c | 0 .../{bradanlane_dck01 => bradanlane_rp2040_dck01}/mpconfigboard.h | 0 .../mpconfigboard.mk | 0 .../pico-sdk-configboard.h | 0 .../boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/pins.c | 0 5 files changed, 0 insertions(+), 0 deletions(-) rename ports/raspberrypi/boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/board.c (100%) rename ports/raspberrypi/boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/mpconfigboard.h (100%) rename ports/raspberrypi/boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/mpconfigboard.mk (100%) rename ports/raspberrypi/boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/pico-sdk-configboard.h (100%) rename ports/raspberrypi/boards/{bradanlane_dck01 => bradanlane_rp2040_dck01}/pins.c (100%) diff --git a/ports/raspberrypi/boards/bradanlane_dck01/board.c b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c similarity index 100% rename from ports/raspberrypi/boards/bradanlane_dck01/board.c rename to ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c diff --git a/ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.h b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h similarity index 100% rename from ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.h rename to ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h diff --git a/ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.mk b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk similarity index 100% rename from ports/raspberrypi/boards/bradanlane_dck01/mpconfigboard.mk rename to ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk diff --git a/ports/raspberrypi/boards/bradanlane_dck01/pico-sdk-configboard.h b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pico-sdk-configboard.h similarity index 100% rename from ports/raspberrypi/boards/bradanlane_dck01/pico-sdk-configboard.h rename to ports/raspberrypi/boards/bradanlane_rp2040_dck01/pico-sdk-configboard.h diff --git a/ports/raspberrypi/boards/bradanlane_dck01/pins.c b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c similarity index 100% rename from ports/raspberrypi/boards/bradanlane_dck01/pins.c rename to ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c From 144362912d0c4be5078f443ec98126dd1c72e268 Mon Sep 17 00:00:00 2001 From: Bradan Lane Date: Thu, 7 Dec 2023 17:10:23 -0500 Subject: [PATCH 9/9] P1 board - epaper not working --- .../boards/bradanlane_rp2040_dck01/board.c | 174 +++++++++--------- .../bradanlane_rp2040_dck01/mpconfigboard.h | 59 ++---- .../bradanlane_rp2040_dck01/mpconfigboard.mk | 5 +- .../boards/bradanlane_rp2040_dck01/pins.c | 61 ++---- 4 files changed, 122 insertions(+), 177 deletions(-) diff --git a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c index 7aa08593156d7..70d81003f4a9c 100644 --- a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c +++ b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/board.c @@ -38,69 +38,69 @@ #define DELAY_FLAG 0x80 #define EPD_RAM_BW 0x10 -#define EPD_RAM_RED 0x13 +#define EPD_RAM_RED 0x13 // #define BUSY_WAIT 500 // These commands are the combination of SSD1608 and SSD1681 and not all commands are supported for each controller -#define SSD_DRIVER_CONTROL 0x01 -#define SSD_GATE_VOLTAGE 0x03 -#define SSD_SOURCE_VOLTAGE 0x04 -#define SSD_DISPLAY_CONTROL 0x07 -#define SSD_PROGOTP_INITIAL 0x08 -#define SSD_WRITEREG_INITIAL 0x09 -#define SSD_READREG_INITIAL 0x0A -#define SSD_NON_OVERLAP 0x0B -#define SSD_BOOST_SOFT_START 0x0C -#define SSD_DEEP_SLEEP 0x10 -#define SSD_DATA_MODE 0x11 -#define SSD_SW_RESET 0x12 -#define SSD_HV_DETECT 0x14 -#define SSD_VCI_DETECT 0x15 -#define SSD1681_TEMP_CONTROL 0x18 -#define SSD1608_TEMP_CONTROL 0x1C -#define SSD_TEMP_WRITE 0x1A -#define SSD_TEMP_READ 0x1B -#define SSD_TEMP_EXTERN 0x1C -#define SSD_MASTER_ACTIVATE 0x20 -#define SSD_DISP_CTRL1 0x21 -#define SSD_DISP_CTRL2 0x22 -#define SSD_WRITE_RAM_BLK 0x24 -// #define SSD_READ_RAM_BLK 0x25 -#define SSD_WRITE_RAM_RED 0x26 -// #define SSD_READ_RAM_RED 0x27 -#define SSD_VCOM_SENSE 0x28 -// #define SSD_VCOM_DURRATION 0x29 -// #define SSD_PROG_VCOM 0x2A -// #define SSD_CTRL_VCOM 0x2B -// #define SSD_WRITE_VCOM 0x2C -#define SSD_READ_OTP 0x2D -#define SSD_READ_ID 0x2E -#define SSD_READ_STATUS 0x2F -#define SSD_WRITE_LUT 0x32 -#define SSD_WRITE_DUMMY 0x3A -#define SSD1608_WRITE_GATELINE 0x3B -#define SSD_WRITE_BORDER 0x3C -#define SSD_SET_RAMXPOS 0x44 -#define SSD_SET_RAMYPOS 0x45 -#define SSD_SET_RAMXCOUNT 0x4E -#define SSD_SET_RAMYCOUNT 0x4F -#define SSD_NOP 0xFF +#define SSD_DRIVER_CONTROL 0x01 +#define SSD_GATE_VOLTAGE 0x03 +#define SSD_SOURCE_VOLTAGE 0x04 +#define SSD_DISPLAY_CONTROL 0x07 +#define SSD_PROGOTP_INITIAL 0x08 +#define SSD_WRITEREG_INITIAL 0x09 +#define SSD_READREG_INITIAL 0x0A +#define SSD_NON_OVERLAP 0x0B +#define SSD_BOOST_SOFT_START 0x0C +#define SSD_DEEP_SLEEP 0x10 +#define SSD_DATA_MODE 0x11 +#define SSD_SW_RESET 0x12 +#define SSD_HV_DETECT 0x14 +#define SSD_VCI_DETECT 0x15 +#define SSD1681_TEMP_CONTROL 0x18 +#define SSD1608_TEMP_CONTROL 0x1C +#define SSD_TEMP_WRITE 0x1A +#define SSD_TEMP_READ 0x1B +#define SSD_TEMP_EXTERN 0x1C +#define SSD_MASTER_ACTIVATE 0x20 +#define SSD_DISP_CTRL1 0x21 +#define SSD_DISP_CTRL2 0x22 +#define SSD_WRITE_RAM_BLK 0x24 +// #define SSD_READ_RAM_BLK 0x25 +#define SSD_WRITE_RAM_RED 0x26 +// #define SSD_READ_RAM_RED 0x27 +#define SSD_VCOM_SENSE 0x28 +// #define SSD_VCOM_DURRATION 0x29 +// #define SSD_PROG_VCOM 0x2A +// #define SSD_CTRL_VCOM 0x2B +// #define SSD_WRITE_VCOM 0x2C +#define SSD_READ_OTP 0x2D +#define SSD_READ_ID 0x2E +#define SSD_READ_STATUS 0x2F +#define SSD_WRITE_LUT 0x32 +#define SSD_WRITE_DUMMY 0x3A +#define SSD1608_WRITE_GATELINE 0x3B +#define SSD_WRITE_BORDER 0x3C +#define SSD_SET_RAMXPOS 0x44 +#define SSD_SET_RAMYPOS 0x45 +#define SSD_SET_RAMXCOUNT 0x4E +#define SSD_SET_RAMYCOUNT 0x4F +#define SSD_NOP 0xFF #define SSD_TEMP_CONTROL SSD1681_TEMP_CONTROL const uint8_t _start_sequence[] = { - SSD_SW_RESET, DELAY_FLAG + 0, 20, // soft reset and wait 20ms - SSD_DATA_MODE, 1, 0x03, // Data entry sequence - SSD_WRITE_BORDER, 1, 0x05, // border color - SSD_TEMP_CONTROL, 1, 0x80, // Temp control - SSD_SET_RAMXCOUNT, 1, 0x00, - SSD_SET_RAMYCOUNT, 2, 0x00, 0x00, - SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), (((WIDTH >> 8) - 1) & 0xFF), 0x00, // set display size - SSD_DISP_CTRL2, 1, 0xf7, // Set DISP only full refreshes + SSD_SW_RESET, DELAY_FLAG + 0, 20, // soft reset and wait 20ms + SSD_DATA_MODE, 1, 0x03, // Data entry sequence + SSD_WRITE_BORDER, 1, 0x05, // border color + SSD_TEMP_CONTROL, 1, 0x80, // Temp control + SSD_SET_RAMXCOUNT, 1, 0x00, + SSD_SET_RAMYCOUNT, 2, 0x00, 0x00, + SSD_DRIVER_CONTROL, 3, ((WIDTH - 1) & 0xFF), (((WIDTH >> 8) - 1) & 0xFF), 0x00, // set display size + SSD_DISP_CTRL2, 1, 0xf7, // Set DISP only full refreshes }; const uint8_t _stop_sequence[] = { - SSD_DEEP_SLEEP, DELAY_FLAG + 1, 1, 0x64 // Enter deep sleep + SSD_DEEP_SLEEP, DELAY_FLAG + 1, 1, 0x64 // Enter deep sleep }; const uint8_t _refresh_sequence[] = { @@ -119,12 +119,12 @@ void board_init(void) { bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, - DEFAULT_SPI_BUS_DC, // EPD_DC Command or data - DEFAULT_SPI_BUS_CS, // EPD_CS Chip select - DEFAULT_SPI_BUS_RESET, // EPD_RST Reset - 1000000, // Baudrate - 0, // Polarity - 0); // Phase + DEFAULT_SPI_BUS_DC, // EPD_DC Command or data + DEFAULT_SPI_BUS_CS, // EPD_CS Chip select + DEFAULT_SPI_BUS_RESET, // EPD_RST Reset + 1000000, // Baudrate + 0, // Polarity + 0); // Phase // Set up the DisplayIO epaper object displayio_epaperdisplay_obj_t *display = &allocate_display()->epaper_display; @@ -134,37 +134,38 @@ void board_init(void) { display, bus, _start_sequence, sizeof(_start_sequence), - 1.0, // start up time + 1.0, // start up time _stop_sequence, sizeof(_stop_sequence), - WIDTH, // width - HEIGHT, // height - WIDTH, // ram_width - HEIGHT + 0x60, // ram_height RAM is actually only 200 bits high but we use 296 to match the 9 bits - 0, // colstart - 0, // rowstart - 0, // rotation - SSD_SET_RAMXPOS, // set_column_window_command - SSD_SET_RAMYPOS, // set_row_window_command - SSD_SET_RAMXCOUNT, // set_current_column_command - SSD_SET_RAMYCOUNT, // set_current_row_command - SSD_WRITE_RAM_BLK, // write_black_ram_command - false, // black_bits_inverted - SSD_WRITE_RAM_RED, // write_color_ram_command - false, // color_bits_inverted - 0xFF0000, // highlight_color (RED for tri-color display) - _refresh_sequence, sizeof(_refresh_sequence), // refresh_display_command - 15.0, // refresh_time - DEFAULT_SPI_BUS_BUSY, // busy_pin - true, // busy_state - 20.0, // seconds_per_frame (does not seem the user can change this) - true, // always_toggle_chip_select - false, // grayscale - false, // acep - false, // two_byte_sequence_length - true); // address_little_endian + WIDTH, // width + HEIGHT, // height + WIDTH, // ram_width + HEIGHT + 0x60, // ram_height RAM is actually only 200 bits high but we use 296 to match the 9 bits + 0, // colstart + 0, // rowstart + 0, // rotation + SSD_SET_RAMXPOS, // set_column_window_command + SSD_SET_RAMYPOS, // set_row_window_command + SSD_SET_RAMXCOUNT, // set_current_column_command + SSD_SET_RAMYCOUNT, // set_current_row_command + SSD_WRITE_RAM_BLK, // write_black_ram_command + false, // black_bits_inverted + SSD_WRITE_RAM_RED, // write_color_ram_command + false, // color_bits_inverted + 0xFF0000, // highlight_color (RED for tri-color display) + _refresh_sequence, sizeof(_refresh_sequence), // refresh_display_command + 15.0, // refresh_time + DEFAULT_SPI_BUS_BUSY, // busy_pin + true, // busy_state + 20.0, // seconds_per_frame (does not seem the user can change this) + true, // always_toggle_chip_select + false, // grayscale + false, // acep + false, // two_byte_sequence_length + true); // address_little_endian } void board_deinit(void) { + #if 0 displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; if (display->base.type == &displayio_epaperdisplay_type) { while (common_hal_displayio_epaperdisplay_get_busy(display)) { @@ -172,6 +173,7 @@ void board_deinit(void) { } } common_hal_displayio_release_displays(); + #endif } // Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. diff --git a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h index a2bef2d7561f1..b44cb56e18a6f 100644 --- a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h +++ b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.h @@ -22,49 +22,20 @@ * THE SOFTWARE. */ +#pragma once #define MICROPY_HW_BOARD_NAME "DCK01" -#define MICROPY_HW_MCU_NAME "rp2040" - -#define DCK01_PROTOTYPE // only needed until the production PCBs are available - - - - -#ifdef DCK01_PROTOTYPE - -// #define MICROPY_HW_LED_STATUS (&pin_GPIO4) - -#define DEFAULT_UART_BUS_TX (&pin_GPIO0) -#define DEFAULT_UART_BUS_RX (&pin_GPIO1) - -#define DEFAULT_I2C_BUS_SDA (&pin_GPIO8) -#define DEFAULT_I2C_BUS_SCL (&pin_GPIO9) - -#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO21) -#define DEFAULT_SPI_BUS_RESET (&pin_GPIO20) -#define DEFAULT_SPI_BUS_DC (&pin_GPIO16) -// #define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) -#define DEFAULT_SPI_BUS_CS (&pin_GPIO17) -#define DEFAULT_SPI_BUS_SCK (&pin_GPIO18) -#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO19) - -#else - -#define MICROPY_HW_LED_STATUS (&pin_GPIO4) - -#define DEFAULT_UART_BUS_TX (&pin_GPIO0) -#define DEFAULT_UART_BUS_RX (&pin_GPIO1) - -#define DEFAULT_I2C_BUS_SDA (&pin_GPIO8) -#define DEFAULT_I2C_BUS_SCL (&pin_GPIO9) - -#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO9) -#define DEFAULT_SPI_BUS_RESET (&pin_GPIO10) -#define DEFAULT_SPI_BUS_DC (&pin_GPIO11) -#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) -#define DEFAULT_SPI_BUS_CS (&pin_GPIO13) -#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) -#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) - -#endif +#define MICROPY_HW_MCU_NAME "rp2040" + +#define MICROPY_HW_LED_STATUS (&pin_GPIO4) +#define DEFAULT_UART_BUS_TX (&pin_GPIO0) +#define DEFAULT_UART_BUS_RX (&pin_GPIO1) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO2) +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO3) +#define DEFAULT_SPI_BUS_BUSY (&pin_GPIO9) +#define DEFAULT_SPI_BUS_RESET (&pin_GPIO10) +#define DEFAULT_SPI_BUS_DC (&pin_GPIO11) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO12) +#define DEFAULT_SPI_BUS_CS (&pin_GPIO13) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO14) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO15) diff --git a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk index e2a22aa0e2a19..8aa3c93b2c191 100644 --- a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk +++ b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/mpconfigboard.mk @@ -1,5 +1,5 @@ -USB_VID = 0x1209 -USB_PID = 0xA182 +USB_VID = 0x2E8A +USB_PID = 0x1073 USB_PRODUCT = "RP2040 DCK01" USB_MANUFACTURER = "Bradán Lane STUDIO" CHIP_VARIANT = RP2040 @@ -9,5 +9,4 @@ EXTERNAL_FLASH_DEVICES = "GD25Q64C" CIRCUITPY__EVE = 1 -FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Display_Text diff --git a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c index 8d0dbad8c57c6..8eecb55e69e8a 100644 --- a/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c +++ b/ports/raspberrypi/boards/bradanlane_rp2040_dck01/pins.c @@ -33,45 +33,29 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP0), MP_ROM_PTR(&pin_GPIO0) }, { MP_ROM_QSTR(MP_QSTR_GP1), MP_ROM_PTR(&pin_GPIO1) }, // GPIO0 and GPIO1 are also the UART - { MP_ROM_QSTR(MP_QSTR_UART_TX), MP_ROM_PTR(&pin_GPIO0) }, - { MP_ROM_QSTR(MP_QSTR_UART_RX), MP_ROM_PTR(&pin_GPIO1) }, + { MP_ROM_QSTR(MP_QSTR_UART_TX), MP_ROM_PTR(DEFAULT_UART_BUS_TX) }, + { MP_ROM_QSTR(MP_QSTR_UART_RX), MP_ROM_PTR(DEFAULT_UART_BUS_RX) }, { MP_ROM_QSTR(MP_QSTR_GP2), MP_ROM_PTR(&pin_GPIO2) }, { MP_ROM_QSTR(MP_QSTR_GP3), MP_ROM_PTR(&pin_GPIO3) }, // GPIO2 and GPIO3 are also the I2C - #ifdef DCK01_PROTOTYPE - { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO8) }, - { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO9) }, - #else - { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO2) }, - { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO3) }, - #endif + { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(DEFAULT_I2C_BUS_SDA) }, + { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(DEFAULT_I2C_BUS_SCL) }, { MP_ROM_QSTR(MP_QSTR_GP4), MP_ROM_PTR(&pin_GPIO4) }, // GPIO4 is also the LED - #ifdef DCK01_PROTOTYPE - // not defined on prototype - #else - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO4) }, - #endif + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(MICROPY_HW_LED_STATUS) }, { MP_ROM_QSTR(MP_QSTR_GP5), MP_ROM_PTR(&pin_GPIO5) }, // GPIO5 is also the NEOPIXEL - #ifdef DCK01_PROTOTYPE - { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO10) }, - #else { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO5) }, - #endif { MP_ROM_QSTR(MP_QSTR_GP6), MP_ROM_PTR(&pin_GPIO6) }, - // GPIO6 is also the speaker (PWM) - #ifdef DCK01_PROTOTYPE + { MP_ROM_QSTR(MP_QSTR_GP7), MP_ROM_PTR(&pin_GPIO7) }, + // GPIO6 is also the speaker (PWM) and GPIO7 is the enable { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPIO6) }, - #else - { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_GPI11) }, - #endif + { MP_ROM_QSTR(MP_QSTR_SPEAKER_EN), MP_ROM_PTR(&pin_GPIO7) }, - { MP_ROM_QSTR(MP_QSTR_GP7), MP_ROM_PTR(&pin_GPIO7) }, { MP_ROM_QSTR(MP_QSTR_GP8), MP_ROM_PTR(&pin_GPIO8) }, { MP_ROM_QSTR(MP_QSTR_GP9), MP_ROM_PTR(&pin_GPIO9) }, @@ -82,29 +66,21 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP14), MP_ROM_PTR(&pin_GPIO14) }, { MP_ROM_QSTR(MP_QSTR_GP15), MP_ROM_PTR(&pin_GPIO15) }, // GPIO9 thru GPIO15 are the SPI for the ePaper display - #ifdef DCK01_PROTOTYPE - // not defined on prototype - #else - { MP_ROM_QSTR(MP_QSTR_SPI_BUSY), MP_ROM_PTR(&pin_GPIO9) }, - { MP_ROM_QSTR(MP_QSTR_SPI_RESET), MP_ROM_PTR(&pin_GPIO10) }, - { MP_ROM_QSTR(MP_QSTR_SPI_DC), MP_ROM_PTR(&pin_GPIO11) }, - { MP_ROM_QSTR(MP_QSTR_SPI_MISO), MP_ROM_PTR(&pin_GPIO12) }, - { MP_ROM_QSTR(MP_QSTR_SPI_CS), MP_ROM_PTR(&pin_GPIO13) }, - { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_GPIO14) }, - { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(&pin_GPIO15) }, - #endif + { MP_ROM_QSTR(MP_QSTR_SPI_BUSY), MP_ROM_PTR(DEFAULT_SPI_BUS_BUSY) }, + { MP_ROM_QSTR(MP_QSTR_SPI_RESET), MP_ROM_PTR(DEFAULT_SPI_BUS_RESET) }, + { MP_ROM_QSTR(MP_QSTR_SPI_DC), MP_ROM_PTR(DEFAULT_SPI_BUS_DC) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MISO), MP_ROM_PTR(DEFAULT_SPI_BUS_MISO) }, + { MP_ROM_QSTR(MP_QSTR_SPI_CS), MP_ROM_PTR(DEFAULT_SPI_BUS_CS) }, + { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(DEFAULT_SPI_BUS_SCK) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(DEFAULT_SPI_BUS_MOSI) }, { MP_ROM_QSTR(MP_QSTR_GP16), MP_ROM_PTR(&pin_GPIO16) }, { MP_ROM_QSTR(MP_QSTR_GP17), MP_ROM_PTR(&pin_GPIO17) }, { MP_ROM_QSTR(MP_QSTR_GP18), MP_ROM_PTR(&pin_GPIO18) }, // GPIO16 thru GPIO18 are also the I2S audio - #ifdef DCK01_PROTOTYPE - // not defined on prototype - #else { MP_ROM_QSTR(MP_QSTR_I2S_DATA), MP_ROM_PTR(&pin_GPIO16) }, { MP_ROM_QSTR(MP_QSTR_I2S_BCK), MP_ROM_PTR(&pin_GPIO17) }, { MP_ROM_QSTR(MP_QSTR_I2S_LRCK), MP_ROM_PTR(&pin_GPIO18) }, - #endif { MP_ROM_QSTR(MP_QSTR_GP19), MP_ROM_PTR(&pin_GPIO19) }, { MP_ROM_QSTR(MP_QSTR_GP20), MP_ROM_PTR(&pin_GPIO20) }, @@ -112,17 +88,13 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_GP22), MP_ROM_PTR(&pin_GPIO22) }, { MP_ROM_QSTR(MP_QSTR_GP23), MP_ROM_PTR(&pin_GPIO23) }, { MP_ROM_QSTR(MP_QSTR_GP24), MP_ROM_PTR(&pin_GPIO24) }, - // GPIO19 thru GPIO24 are also the touch pads - #ifdef DCK01_PROTOTYPE - // not defined on prototype - #else + // GPIO19 thru GPIO24 are also the touch sensors { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_GPIO19) }, { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_GPIO20) }, { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_GPIO21) }, { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_GPIO22) }, { MP_ROM_QSTR(MP_QSTR_TOUCH5), MP_ROM_PTR(&pin_GPIO23) }, { MP_ROM_QSTR(MP_QSTR_TOUCH6), MP_ROM_PTR(&pin_GPIO24) }, - #endif { MP_ROM_QSTR(MP_QSTR_GP25), MP_ROM_PTR(&pin_GPIO25) }, @@ -143,4 +115,5 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].epaper_display)}, }; + MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);