From 3a42578d477249cc8851cd76cfb4fa4cb88ab0a0 Mon Sep 17 00:00:00 2001 From: Andy Nichols Date: Mon, 28 May 2012 16:42:39 +0200 Subject: [PATCH] [PATCH] [V8] Add support for using armv6 vfp2 instructions This is needed when building for armv6 with the hardfloat ABI. --- deps/v8/src/arm/assembler-arm.cc | 15 +++++++++------ deps/v8/src/arm/code-stubs-arm.cc | 8 ++++---- deps/v8/src/arm/macro-assembler-arm.cc | 8 ++++---- deps/v8/src/v8globals.h | 1 + 4 files changed, 18 insertions(+), 14 deletions(-) diff --git a/deps/v8/src/arm/assembler-arm.cc b/deps/v8/src/arm/assembler-arm.cc index ec28da40025..922eec48579 100644 --- a/deps/v8/src/arm/assembler-arm.cc +++ b/deps/v8/src/arm/assembler-arm.cc @@ -52,7 +52,7 @@ unsigned CpuFeatures::found_by_runtime_probing_ = 0; // Get the CPU features enabled by the build. For cross compilation the -// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP_INSTRUCTIONS +// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS // can be defined to enable ARMv7 and VFPv3 instructions when building the // snapshot. static uint64_t CpuFeaturesImpliedByCompiler() { @@ -60,9 +60,12 @@ static uint64_t CpuFeaturesImpliedByCompiler() { #ifdef CAN_USE_ARMV7_INSTRUCTIONS answer |= 1u << ARMv7; #endif // def CAN_USE_ARMV7_INSTRUCTIONS -#ifdef CAN_USE_VFP_INSTRUCTIONS - answer |= 1u << VFP3 | 1u << ARMv7; -#endif // def CAN_USE_VFP_INSTRUCTIONS +#ifdef CAN_USE_VFP3_INSTRUCTIONS + answer |= 1u << VFP3 | 1u << VFP2 | 1u << ARMv7; +#endif // def CAN_USE_VFP3_INSTRUCTIONS +#ifdef CAN_USE_VFP2_INSTRUCTIONS + answer |= 1u << VFP2; +#endif // def CAN_USE_VFP2_INSTRUCTIONS #ifdef __arm__ // If the compiler is allowed to use VFP then we can use VFP too in our code @@ -1742,7 +1745,7 @@ void Assembler::vstr(const DwVfpRegister src, // Instruction details available in ARM DDI 0406A, A8-786. // cond(31-28) | 1101(27-24)| U000(23-20) | | Rbase(19-16) | // Vsrc(15-12) | 1011(11-8) | (offset/4) - ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3) || CpuFeatures::IsEnabled(VFP2)); int u = 1; if (offset < 0) { offset = -offset; @@ -2028,7 +2031,7 @@ void Assembler::vmov(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-646. // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm - ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3) || CpuFeatures::IsEnabled(VFP2)); ASSERT(!src1.is(pc) && !src2.is(pc)); emit(cond | 0xC*B24 | B22 | src2.code()*B16 | src1.code()*B12 | 0xB*B8 | B4 | dst.code()); diff --git a/deps/v8/src/arm/code-stubs-arm.cc b/deps/v8/src/arm/code-stubs-arm.cc index 761123f6393..db3dd93be72 100644 --- a/deps/v8/src/arm/code-stubs-arm.cc +++ b/deps/v8/src/arm/code-stubs-arm.cc @@ -978,7 +978,7 @@ void FloatingPointHelper::CallCCodeForDoubleOperation( __ push(lr); __ PrepareCallCFunction(0, 2, scratch); if (masm->use_eabi_hardfloat()) { - CpuFeatures::Scope scope(VFP3); + CpuFeatures::Scope scope(VFP2); __ vmov(d0, r0, r1); __ vmov(d1, r2, r3); } @@ -990,7 +990,7 @@ void FloatingPointHelper::CallCCodeForDoubleOperation( // Store answer in the overwritable heap number. Double returned in // registers r0 and r1 or in d0. if (masm->use_eabi_hardfloat()) { - CpuFeatures::Scope scope(VFP3); + CpuFeatures::Scope scope(VFP2); __ vstr(d0, FieldMemOperand(heap_number_result, HeapNumber::kValueOffset)); } else { @@ -1362,7 +1362,7 @@ static void EmitTwoNonNanDoubleComparison(MacroAssembler* masm, __ push(lr); __ PrepareCallCFunction(0, 2, r5); if (masm->use_eabi_hardfloat()) { - CpuFeatures::Scope scope(VFP3); + CpuFeatures::Scope scope(VFP2); __ vmov(d0, r0, r1); __ vmov(d1, r2, r3); } @@ -3389,7 +3389,7 @@ void TranscendentalCacheStub::GenerateCallCFunction(MacroAssembler* masm, __ push(lr); __ PrepareCallCFunction(0, 1, scratch); - if (masm->use_eabi_hardfloat()) { + if (masm->use_eabi_hardfloat() && CpuFeatures::IsSupported(VFP3)) { __ vmov(d0, d2); } else { __ vmov(r0, r1, d2); diff --git a/deps/v8/src/arm/macro-assembler-arm.cc b/deps/v8/src/arm/macro-assembler-arm.cc index 933399e00f4..f84a34038cb 100644 --- a/deps/v8/src/arm/macro-assembler-arm.cc +++ b/deps/v8/src/arm/macro-assembler-arm.cc @@ -930,7 +930,7 @@ void MacroAssembler::LeaveExitFrame(bool save_doubles, } void MacroAssembler::GetCFunctionDoubleResult(const DoubleRegister dst) { - if (use_eabi_hardfloat()) { + if (use_eabi_hardfloat() && CpuFeatures::IsSupported(VFP3)) { Move(dst, d0); } else { vmov(dst, r0, r1); @@ -3332,7 +3332,7 @@ void MacroAssembler::PrepareCallCFunction(int num_reg_arguments, void MacroAssembler::SetCallCDoubleArguments(DoubleRegister dreg) { - if (use_eabi_hardfloat()) { + if (use_eabi_hardfloat() && CpuFeatures::IsSupported(VFP3)) { Move(d0, dreg); } else { vmov(r0, r1, dreg); @@ -3342,7 +3342,7 @@ void MacroAssembler::SetCallCDoubleArguments(DoubleRegister dreg) { void MacroAssembler::SetCallCDoubleArguments(DoubleRegister dreg1, DoubleRegister dreg2) { - if (use_eabi_hardfloat()) { + if (use_eabi_hardfloat() && CpuFeatures::IsSupported(VFP3)) { if (dreg2.is(d0)) { ASSERT(!dreg1.is(d1)); Move(d1, dreg2); @@ -3360,7 +3360,7 @@ void MacroAssembler::SetCallCDoubleArguments(DoubleRegister dreg1, void MacroAssembler::SetCallCDoubleArguments(DoubleRegister dreg, Register reg) { - if (use_eabi_hardfloat()) { + if (use_eabi_hardfloat() && CpuFeatures::IsSupported(VFP3)) { Move(d0, dreg); Move(r0, reg); } else { diff --git a/deps/v8/src/v8globals.h b/deps/v8/src/v8globals.h index 6a1766a1a58..1868b9184c0 100644 --- a/deps/v8/src/v8globals.h +++ b/deps/v8/src/v8globals.h @@ -442,6 +442,7 @@ enum CpuFeature { SSE4_1 = 32 + 19, // x86 CPUID = 10, // x86 VFP3 = 1, // ARM ARMv7 = 2, // ARM + VFP2 = 4, // ARM SAHF = 0, // x86 FPU = 1}; // MIPS