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Branch: qom-cpu-ppc
Commits on Aug 28, 2015
  1. disas: alpha: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() alpha specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    This also makes monitor_disas() consistent with target_disas(), as
    monitor_disas() was missing a set of the BFD (This was an omission from
    commit b9bec75).
    
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Acked-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  2. disas: mips: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() mips specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Cc: Aurelien Jarno <aurelien@aurel32.net>
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Acked-by: Leon Alrae <leon.alrae@imgtec.com>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  3. disas: sh4: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() sh4 specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Acked-by: Aurelien Jarno <aurelien@aurel32.net>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  4. disas: lm32: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() lm32 specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Acked-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  5. disas: sparc: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() sparc specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  6. disas: m68k: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() m68k specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Reviewed-by: Laurent Vivier <laurent@vivier.eu>
    Reviewed-by: Greg Ungerer <gerg@uclinux.org>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  7. disas: moxie: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() moxie specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Cc: Anthony Green <green@moxielogic.com>
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  8. disas: s390x: QOMify target specific disas setup

    Peter Crosthwaite authored committed
    Move the target_disas() s390 specifics to the QOM disas_set_info hook
    and delete the #ifdef specific code in disas.c.
    
    Cc: Alexander Graf <agraf@suse.de>
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
    Acked-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  9. @vivier @pm215

    s390: fix softmmu compilation

    vivier authored pm215 committed
    guest_base must be used only in linux-user mode.
    
    Signed-off-by: Laurent Vivier <laurent@vivier.eu>
    Message-id: 1440757421-9674-1-git-send-email-laurent@vivier.eu
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  10. @pm215

    qemu-doc.texi: Fix capitalization error in OS X build instructions

    pm215 authored
    Fix a capitalization error in the OS X build instructions;
    this was picked up in review of commit b352153 and intended to be
    corrected before I applied it, but I accidentally didn't include it.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commits on Aug 27, 2015
  1. @pm215

    From: John Arbuckle <programmingkidx@gmail.com>

    G 3 authored pm215 committed
    qemu-doc.texi: Add information on compiling source code on Mac OS X
    
    Add information to the documentation on how to build QEMU
    on Mac OS X.
    
    Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    [PMM: fixed a minor capitalization error]
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  2. @pm215

    Merge remote-tracking branch 'remotes/weil/tags/pull-tci-20150826' in…

    pm215 authored
    …to staging
    
    tci patch queue
    
    # gpg: Signature made Wed 26 Aug 2015 19:51:07 BST using RSA key ID 677450AD
    # gpg: Good signature from "Stefan Weil <sw@weilnetz.de>"
    # gpg:                 aka "Stefan Weil <stefan.weil@weilnetz.de>"
    # gpg:                 aka "Stefan Weil <stefan.weil@bib.uni-mannheim.de>"
    # gpg: WARNING: This key is not certified with a trusted signature!
    # gpg:          There is no indication that the signature belongs to the owner.
    # Primary key fingerprint: 4923 6FEA 75C9 5D69 8EC2  B78A E08C 21D5 6774 50AD
    
    * remotes/weil/tags/pull-tci-20150826:
      exec-all: Translate TCI return addresses backwards too
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commits on Aug 26, 2015
  1. @stweil

    exec-all: Translate TCI return addresses backwards too

    Peter Crosthwaite authored stweil committed
    This subtraction of return addresses applies directly to TCI as well as
    host-TCG. This fixes Linux boots for at least Microblaze, CRIS, ARM and
    SH4 when using TCI.
    
    [sw: Removed indentation for preprocessor statement]
    [sw: The patch also fixes Linux boot for x86_64]
    
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Stefan Weil <sw@weilnetz.de>
    Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
  2. @pm215

    Merge remote-tracking branch 'remotes/kraxel/tags/pull-cve-2015-5225-…

    pm215 authored
    …20150826-1' into staging
    
    vnc: fix memory corruption (CVE-2015-5225)
    
    # gpg: Signature made Wed 26 Aug 2015 17:37:21 BST using RSA key ID D3E87138
    # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
    # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
    # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
    
    * remotes/kraxel/tags/pull-cve-2015-5225-20150826-1:
      vnc: fix memory corruption (CVE-2015-5225)
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  3. @kraxel

    vnc: fix memory corruption (CVE-2015-5225)

    kraxel authored
    The _cmp_bytes variable added by commit "bea60dd ui/vnc: fix potential
    memory corruption issues" can become negative.  Result is (possibly
    exploitable) memory corruption.  Reason for that is it uses the stride
    instead of bytes per scanline to apply limits.
    
    For the server surface is is actually fine.  vnc creates that itself,
    there is never any padding and thus scanline length always equals stride.
    
    For the guest surface scanline length and stride are typically identical
    too, but it doesn't has to be that way.  So add and use a new variable
    (guest_ll) for the guest scanline length.  Also rename min_stride to
    line_bytes to make more clear what it actually is.  Finally sprinkle
    in an assert() to make sure we never use a negative _cmp_bytes again.
    
    Reported-by: 范祚至(库特) <zuozhi.fzz@alibaba-inc.com>
    Reviewed-by: P J P <ppandit@redhat.com>
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commits on Aug 25, 2015
  1. @pm215

    Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-2…

    pm215 authored
    …0150825-1' into staging
    
    target-arm queue:
     * add missing EL2/EL3 TLBI operations
     * add missing EL2/EL3 ATS operations
     * add missing EL2/EL3 registers
     * update Xilinx MAINTAINERS info
     * Xilinx: connect the four OCM banks
    
    # gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE
    # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
    # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
    # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
    
    * remotes/pmaydell/tags/pull-target-arm-20150825-1:
      target-arm: Implement AArch64 TLBI operations on IPAs
      target-arm: Implement missing EL3 TLB invalidate operations
      target-arm: Implement missing EL2 TLBI operations
      target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
      target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
      cputlb: Add functions for flushing TLB for a single MMU index
      target-arm: Implement AArch32 ATS1H* operations
      target-arm: Enable the AArch32 ATS12NSO ops
      target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
      target-arm: Wire up AArch64 EL2 and EL3 address translation ops
      target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
      target-arm: Implement missing ACTLR registers
      target-arm: Implement missing AFSR registers
      target-arm: Implement missing AMAIR registers
      target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
      MAINTAINERS: Add ZynqMP to MAINTAINERS file
      MAINTAINERS: Update Xilinx Maintainership
      xlnx-zynqmp: Connect the four OCM banks
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  2. @pm215

    target-arm: Implement AArch64 TLBI operations on IPAs

    pm215 authored
    Implement the AArch64 TLBI operations which take an intermediate
    physical address and invalidate stage 2 translations.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
  3. @pm215

    target-arm: Implement missing EL3 TLB invalidate operations

    pm215 authored
    Implement the remaining stage 1 TLB invalidate operations
    visible from EL3.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
  4. @pm215

    target-arm: Implement missing EL2 TLBI operations

    pm215 authored
    Implement the missing TLBI operations that exist only
    if EL2 is implemented.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-5-git-send-email-peter.maydell@linaro.org
  5. @pm215

    target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must…

    pm215 authored
    … touch
    
    Now we have the ability to flush the TLB only for specific MMU indexes,
    update the AArch64 TLB maintenance instruction implementations to only
    flush the parts of the TLB they need to, rather than doing full flushes.
    
    We take the opportunity to remove some duplicate functions (the per-asid
    tlb ops work like the non-per-asid ones because we don't support
    flushing a TLB only by ASID) and to bring the function names in line
    with the architectural TLBI operation names.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-4-git-send-email-peter.maydell@linaro.org
  6. @pm215

    target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order

    pm215 authored
    Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
    whole set of AArch64 TLBI regdefs is arranged in numeric order.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-3-git-send-email-peter.maydell@linaro.org
  7. @pm215

    cputlb: Add functions for flushing TLB for a single MMU index

    pm215 authored
    Guest CPU TLB maintenance operations may be sufficiently
    specialized to only need to flush TLB entries corresponding
    to a particular MMU index. Implement cputlb functions for
    this, to avoid the inefficiency of flushing TLB entries
    which we don't need to.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1439548879-1972-2-git-send-email-peter.maydell@linaro.org
  8. @pm215

    target-arm: Implement AArch32 ATS1H* operations

    pm215 authored
    Implement the AArch32 ATS1H* operations which perform
    Hyp mode stage 1 translations.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org
  9. @pm215

    target-arm: Enable the AArch32 ATS12NSO ops

    pm215 authored
    Apply the correct conditions in the ats_access() function for
    the ATS12NSO* address translation operations:
     * succeed at EL2 or EL3
     * normal UNDEF trap from NS EL1
     * trap to EL3 from S EL1 (only possible if EL3 is AArch64)
    
    (This change means they're now available in our EL3-supporting
    CPUs when they would previously always UNDEF.)
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
  10. @pm215

    target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3

    pm215 authored
    Some coprocessor register access functions need to be able
    to report "trap to EL3 with an 'uncategorized' syndrome";
    add the necessary CPAccessResult enum and handling for it.
    
    I don't currently know of any registers that need to trap
    to EL2 with the 'uncategorized' syndrome, but adding the
    _EL2 enum as well is trivial and fills in what would
    otherwise be an odd gap in the handling.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1437751263-21913-4-git-send-email-peter.maydell@linaro.org
  11. @pm215

    target-arm: Wire up AArch64 EL2 and EL3 address translation ops

    pm215 authored
    Wire up the AArch64 EL2 and EL3 address translation operations
    (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
    errors in the ats_write64() function in previously unused code
    that would have done the wrong kind of lookup for accesses from
    EL3 when SCR.NS==0.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1437751263-21913-3-git-send-email-peter.maydell@linaro.org
  12. @pm215

    target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations

    pm215 authored
    For EL2 stage 1 translations, there is no TTBR1. We were already
    handling this for 64-bit EL2; add the code to take the 'no TTBR1'
    code path for 64-bit EL2 as well.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1437751263-21913-2-git-send-email-peter.maydell@linaro.org
  13. @pm215

    target-arm: Implement missing ACTLR registers

    pm215 authored
    We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
    ACTLR_EL3, for consistency.
    
    Since we don't currently have any CPUs that need the EL2/EL3
    versions to reset to non-zero values, implement as RAZ/WI.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
  14. @pm215

    target-arm: Implement missing AFSR registers

    pm215 authored
    The AFSR registers are implementation dependent auxiliary fault
    status registers. We already implemented a RAZ/WI AFSR0_EL1 and
    AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org
  15. @pm215

    target-arm: Implement missing AMAIR registers

    pm215 authored
    The AMAIR registers are for providing auxiliary implementation
    defined memory attributes. We already implemented a RAZ/WI
    AMAIR_EL1; add the EL2 and EL3 versions for consistency.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1438281398-18746-3-git-send-email-peter.maydell@linaro.org
  16. @pm215

    target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers

    pm215 authored
    Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
    two which we had implemented the 32-bit Secure equivalents of but
    not the 64-bit Secure versions.
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
    Message-id: 1438281398-18746-2-git-send-email-peter.maydell@linaro.org
  17. @alistair23 @pm215

    MAINTAINERS: Add ZynqMP to MAINTAINERS file

    alistair23 authored pm215 committed
    Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers
    file.
    
    Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
    Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    Message-id: fed078103a0b02cfb3adadbe8e80e4420d554505.1436486024.git.alistair.francis@xilinx.com
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  18. @alistair23 @pm215

    MAINTAINERS: Update Xilinx Maintainership

    alistair23 authored pm215 committed
    Peter C is leaving Xilinx, so update the maintainer list
    to point to Alistair and Edgar from Xilinx and Peter's
    personal email address.
    
    Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
    Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    Message-id: 54b4c070452bac05aa3a9c1d75899bc097fef831.1436486024.git.alistair.francis@xilinx.com
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  19. @alistair23 @pm215

    xlnx-zynqmp: Connect the four OCM banks

    alistair23 authored pm215 committed
    The Xilinx EP108 has four separate OCM banks which are located
    adjacent to each other. This patch adds the four banks to
    the ZynqMP SoC.
    
    Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
    Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    Message-id: afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.francis@xilinx.com
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  20. @pm215

    Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' int…

    pm215 authored
    …o staging
    
    queued tcg patches
    
    # gpg: Signature made Mon 24 Aug 2015 19:37:15 BST using RSA key ID 4DD0279B
    # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
    # gpg:                 aka "Richard Henderson <rth@redhat.com>"
    # gpg:                 aka "Richard Henderson <rth@twiddle.net>"
    
    * remotes/rth/tags/pull-tcg-20150824:
      linux-user: remove useless macros GUEST_BASE and RESERVED_VA
      linux-user: remove --enable-guest-base/--disable-guest-base
      tcg/aarch64: Use softmmu fast path for unaligned accesses
      tcg/s390: Use softmmu fast path for unaligned accesses
      tcg/ppc: Improve unaligned load/store handling on 64-bit backend
      tcg/i386: use softmmu fast path for unaligned accesses
      tcg: Remove tcg_gen_trunc_i64_i32
      tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32
      tcg: update README about size changing ops
      tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops
      tcg: implement real ext_i32_i64 and extu_i32_i64 ops
      tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32
      tcg: rename trunc_shr_i32 into trunc_shr_i64_i32
      tcg/optimize: allow constant to have copies
      tcg/optimize: track const/copy status separately
      tcg/optimize: add temp_is_const and temp_is_copy functions
      tcg/optimize: optimize temps tracking
      tcg/optimize: fix constant signedness
    
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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