Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
branch: qom-cpu-vmstat…
Commits on Feb 2, 2013
  1. cpu: Guard cpu_{save,load}() definitions

    authored
    A few targets already managed to implement cpu_save() and cpu_load()
    without defining CPU_SAVE_VERSION that causes them to be registered.
    
    Guard the prototypes with CPU_SAVE_VERSION to avoid this happening again
    until all targets are converted to VMState or QIDL.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  2. target-openrisc: Register VMStateDescription for OpenRISCCPU

    authored
    Since commit e67db06 (target-or32: Add
    target stubs and QOM cpu) a VMStateDescription existed, but
    CPU_SAVE_VERSION was not set, so it was never registered.
    
    Register it through CPUState.
    Use a version_id of 1 and specify minimum versions as well.
    
    Cc: Jia Liu <proljc@gmail.com>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  3. target-alpha: Register VMStateDescription for AlphaCPU

    authored
    Commit b758aca (target-alpha: Enable
    the alpha-softmmu target.) introduced cpu_{save,load}() functions but
    didn't define CPU_SAVE_VERSION, so they were never registered.
    
    Drop cpu_{save,load}() and register the VMStateDescription via CPUClass.
    This operates on the AlphaCPU object instead of CPUAlphaState.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  4. target-lm32: Update VMStateDescription to LM32CPU

    authored
    Expose vmstate_cpu as vmstate_lm32_cpu and hook it up to CPUClass::vmsd.
    Adapt VMState fields to LM32CPU. Drop cpu_{save,load}().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  5. target-i386: Update VMStateDescription to X86CPU

    authored
    Expose vmstate_cpu as vmstate_x86_cpu and hook it up to CPUClass::vmsd.
    Adapt opaques and VMState fields to X86CPU. Drop cpu_{save,load}().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  6. cpu: Register VMStateDescription through CPUState

    authored
    In comparison to DeviceClass::vmsd, CPU VMState is split in two,
    "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
    Therefore add a CPU-specific CPUClass::vmsd field.
    
    Unlike the legacy CPUArchState registration, rather register CPUState.
    
    Signed-off-by: Juan Quintela <quintela@redhat.com>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  7. target-m68k: Pass M68kCPU to m68k_set_irq_level()

    authored
    Simplifies use of cpu_reset_interrupt() et al.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  8. mcf_intc: Pass M68kCPU to mcf_intc_init()

    authored
    Store it in mcf_intc_state.
    Prepares for passing it to m68k_set_irq_level().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  9. mcf5206: Pass M68kCPU to mcf5206_init()

    authored
    Store it in m5206_mbar_state. Prepares for passing M68kCPU to
    m68k_set_irq_level().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  10. target-m68k: Return M68kCPU from cpu_m68k_init()

    authored
    Turn cpu_init() into a static inline function for backwards
    compatibility.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  11. ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()

    authored
    Prepares for changing cpu_interrupt() argument to CPUState.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
    Acked-by: Alexander Graf <agraf@suse.de>
  12. target-xtensa: Move TCG initialization to XtensaCPU initfn

    authored
    Combine this with breakpoint handler registration, guarding both with
    tcg_enabled() to suppress also TCG init for qtest. Rename the handler to
    xtensa_breakpoint_handler() since it needs to become global.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  13. target-unicore32: Move TCG initialization to UniCore32CPU initfn

    authored
    Normalize the "inited" logic and add a tcg_enabled() check to suppress
    it for qtest.
    
    Ensures that a QOM-created UniCore32CPU is usable.
    
    Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  14. target-sparc: Move TCG initialization to SPARCCPU initfn

    authored
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  15. target-sh4: Move TCG initialization to SuperHCPU initfn

    authored
    Add a tcg_enabled() check to suppress it for qtest.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  16. target-s390x: Move TCG initialization to S390CPU initfn

    authored
    Ensures that a QOM-created S390CPU is usable.
    
    Acked-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  17. target-ppc: Move TCG initialization to PowerPCCPU initfn

    authored
    Ensures that a QOM-created PowerPCCPU is usable.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  18. target-mips: Move TCG initialization to MIPSCPU initfn

    authored
    Make mips_tcg_init() non-static and add tcg_enabled() check to suppress
    it for qtest.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  19. target-microblaze: Move TCG initialization to MicroBlazeCPU initfn

    authored
    Split off TCG initialization from cpu_mb_init() into mb_tcg_init() to
    call it from the initfn.
    
    Ensures that a QOM-created MicroBlazeCPU is usable.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  20. target-m68k: Move TCG initialization to M68kCPU initfn

    authored
    Add a tcg_enabled() check to suppress it for qtest.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  21. target-lm32: Move TCG initialization to LM32CPU initfn

    authored
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  22. target-cris: Move TCG initialization to CRISCPU initfn

    authored
    Split out TCG initialization from cpu_cris_init(). Avoid CPUCRISState
    dependency for v10-specific initialization and for non-v10 by inlining
    the decision into the initfn as well.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  23. target-arm: Move TCG initialization to ARMCPU initfn

    authored
    Ensures that a QOM-created ARMCPU is usable.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  24. target-xtensa: Introduce QOM realizefn for XtensaCPU

    authored
    Introduce realizefn and set realized = true in cpu_xtensa_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  25. target-unicore32: Introduce QOM realizefn for UniCore32CPU

    authored
    Introduce a realizefn and set realized = true in uc32_cpu_init().
    
    Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
    [AF: Invoke the parent's realizefn]
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  26. target-sparc: Introduce QOM realizefn for SPARCCPU

    authored
    Introduce realizefn and set realized = true in cpu_sparc_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  27. target-sh4: Introduce QOM realizefn for SuperHCPU

    authored
    Introduce a realizefn and set realized = true in cpu_sh4_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  28. target-s390x: Introduce QOM realizefn for S390CPU

    authored
    Introduce realizefn and set realized = true in cpu_s390x_init().
    
    Defer CPU reset from initfn to realizefn.
    
    Acked-by: Richard Henderson <rth@twiddle.net>
    [AF: Invoke parent's realizefn]
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  29. target-mips: Introduce QOM realizefn for MIPSCPU

    authored
    Introduce a realizefn and set realized = true from cpu_mips_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  30. target-microblaze: Introduce QOM realizefn for MicroBlazeCPU

    authored
    Introduce realizefn and set realized = true from cpu_mb_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  31. target-m68k: Introduce QOM realizefn for M68kCPU

    authored
    Introduce realizefn and set realized = true in cpu_m68k_init().
    
    Split off GDB registration to a new m68k_cpu_init_gdb() so that it can
    be called from the realizefn.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  32. target-lm32: Introduce QOM realizefn for LM32CPU

    authored
    Introduce a realizefn and set realized = true in cpu_lm32_init().
    
    Also move cpu_reset() call from initfn to realizefn.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  33. target-cris: Introduce QOM realizefn for CRISCPU

    authored
    Introduce realizefn and set realized = true from cpu_cris_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  34. target-ppc: Update PowerPCCPU to QOM realizefn

    authored
    Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set
    realized = true in cpu_ppc_init().
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
  35. target-openrisc: Update OpenRISCCPU to QOM realizefn

    authored
    Update the openrisc_cpu_realize() signature, hook it up to
    DeviceClass::realize and set realized = true in cpu_openrisc_init().
    
    qapi/error.h is now included through qdev and no longer needed.
    
    Signed-off-by: Andreas Färber <afaerber@suse.de>
    Cc: Jia Liu <proljc@gmail.com>
Something went wrong with that request. Please try again.