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Commits on Dec 22, 2013
  1. PPC: Fix compilation with TCG debug

    agraf authored and aurel32 committed Dec 20, 2013
    The recent VSX patches broken compilation of QEMU when configurated
    with --enable-debug, as it was treating "target long" TCG variables
    as "i64" which is not true for 32bit targets.
    
    This patch fixes all the places that the compiler has found to use
    the correct variable type and if necessary manually cast.
    
    Reported-by: Stefan Weil <sw@weilnetz.de>
    Signed-off-by: Alexander Graf <agraf@suse.de>
    Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Commits on Dec 21, 2013
  1. Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu

    aurel32 committed Dec 21, 2013
    Patch queue for s390 - 2013-12-18
    
    This covers mostly minor bug fixes and implements the SIGP START
    hypercall which allows to start a remote CPU without changing its
    state.
    
    Cornelia Huck (1):
          s390x/kvm: Fix diagnose handling.
    
    Thomas Huth (7):
          s390x/kvm: Removed duplicated SIGP defines
          s390x/kvm: Removed s390_store_status stub
          s390x/kvm: Fix coding style in handle_sigp()
          s390x/kvm: Implemented SIGP START
          s390x/kvm: Simplified the calculation of the SIGP order code
          s390x/kvm: Fixed condition code for unknown SIGP orders
          s390x/ioinst: CHSC has to set a condition code
    
    * tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu:
      s390x/ioinst: CHSC has to set a condition code
      s390x/kvm: Fixed condition code for unknown SIGP orders
      s390x/kvm: Simplified the calculation of the SIGP order code
      s390x/kvm: Implemented SIGP START
      s390x/kvm: Fix coding style in handle_sigp()
      s390x/kvm: Removed s390_store_status stub
      s390x/kvm: Removed duplicated SIGP defines
      s390x/kvm: Fix diagnose handling.
  2. target-sh4: Use new qemu_ld/st opcodes

    aurel32 committed Dec 11, 2013
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  3. target-mips: Use new qemu_ld/st opcodes

    aurel32 committed Dec 11, 2013
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  4. tcg/i386: fix a comment

    aurel32 committed Dec 10, 2013
    The comments apply to 8-bit stores, not 8-byte stores.
    
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Commits on Dec 20, 2013
  1. Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' int…

    Anthony Liguori
    Anthony Liguori committed Dec 20, 2013
    …o staging
    
    Patch queue for ppc - 2013-12-20
    
    Alexander Graf (3):
          PPC: Use default pci bus name for grackle and heathrow
          roms: Flush icache when writing roms to guest memory
          PPC: Add VSX to hflags
    
    Alexey Kardashevskiy (5):
          powerpc: add PVR mask support
          target-ppc: move POWER7+ to a separate family
          spapr-rtas: replace return code constants with macros
          spapr-rtas: add ibm, (get|set)-system-parameter
          spapr: make sure RMA is in first mode of first memory node
    
    Greg Kurz (1):
          target-ppc: add stubs for KVM breakpoints
    
    Paolo Bonzini (1):
          spapr: tie spapr-nvram to -pflash
    
    Paul Mackerras (1):
          spapr: limit numa memory regions by ram size
    
    Peter Crosthwaite (2):
          device_tree: s/qemu_devtree/qemu_fdt globally
          device_tree: qemu_fdt_setprop: Rename val_array arg
    
    Tom Musta (19):
          Declare and Enable VSX
          Add MSR VSX and Associated Exception
          Add VSX Instruction Decoders
          Add VSR to Global Registers
          Add lxvd2x
          Add stxvd2x
          Add xxpermdi
          Add lxsdx
          Add lxvdsx
          Add lxvw4x
          Add stxsdx
          Add stxvw4x
          Add VSX Scalar Move Instructions
          Add VSX Vector Move Instructions
          Add Power7 VSX Logical Instructions
          Add xxmrgh/xxmrgl
          Add xxsel
          Add xxspltw
          Add xxsldwi
    
    * agraf/tags/signed-ppc-for-upstream: (32 commits)
      spapr: limit numa memory regions by ram size
      spapr: make sure RMA is in first mode of first memory node
      device_tree: qemu_fdt_setprop: Rename val_array arg
      device_tree: s/qemu_devtree/qemu_fdt globally
      PPC: Add VSX to hflags
      Add xxsldwi
      Add xxspltw
      Add xxsel
      Add xxmrgh/xxmrgl
      Add Power7 VSX Logical Instructions
      Add VSX Vector Move Instructions
      Add VSX Scalar Move Instructions
      roms: Flush icache when writing roms to guest memory
      spapr: tie spapr-nvram to -pflash
      PPC: Use default pci bus name for grackle and heathrow
      spapr-rtas: add ibm, (get|set)-system-parameter
      spapr-rtas: replace return code constants with macros
      target-ppc: move POWER7+ to a separate family
      Add stxvw4x
      Add stxsdx
      ...
  2. spapr: limit numa memory regions by ram size

    paulusmack authored and agraf committed Nov 25, 2013
    This makes sure that all NUMA memory blocks reside within RAM or
    have zero length.
    
    Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  3. spapr: make sure RMA is in first mode of first memory node

    aik authored and agraf committed Nov 25, 2013
    The SPAPR specification says that the RMA starts at the LPAR's logical
    address 0 and is the first logical memory block reported in
    the LPAR’s device tree.
    
    So SLOF only maps the first block and that block needs to span
    the full RMA.
    
    This makes sure that the RMA area is where SLOF expects it.
    
    Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  4. device_tree: qemu_fdt_setprop: Rename val_array arg

    pete128 authored and agraf committed Nov 11, 2013
    Looking at the implementation, this doesn't really have a lot to do
    with arrays. Its just a pointer to a buffer and is passed through
    to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it
    consistent with libfdt, which in the wrapped function just calls it
    "val".
    
    Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  5. device_tree: s/qemu_devtree/qemu_fdt globally

    pete128 authored and agraf committed Nov 11, 2013
    The qemu_devtree API is a wrapper around the fdt_ set of APIs.
    Rename accordingly.
    
    Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    [agraf: also convert hw/arm/virt.c]
    Signed-off-by: Alexander Graf <agraf@suse.de>
  6. PPC: Add VSX to hflags

    agraf committed Dec 18, 2013
    We generate different code depending on whether MSR_VSX is set or
    clear, so it needs to be part of our hflags too which indicate whether
    we're still in the same translation block cache bucket.
    
    Signed-off-by: Alexander Graf <agraf@suse.de>
  7. Add xxsldwi

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX Shift Left Double by Word Immediate
    (xxsldwi) instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  8. Add xxspltw

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX Splat Word (xxsplatw) instruction.
    
    This is the first instruction to use the UIM immediate field
    and consequently a decoder is also added.
    
    V2: reworked implementation per Richard Henderson's comments.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  9. Add xxsel

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX Select (xxsel) instruction.
    
    The xxsel instruction has four VSR operands.  Thus the xC
    instruction decoder is added.
    
    The xxsel instruction is massively overloaded in the opcode
    table since only bits 26 and 27 are opcode bits.  This
    overloading is done in matrix fashion with two macros
    (GEN_XXSEL_ROW and GEN_XX_SEL).
    
    V2: (1) eliminated unecessary XXSEL macro  (2) tighter implementation
    using tcg_gen_andc_i64.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  10. Add xxmrgh/xxmrgl

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX Merge High Word and VSX Merge Low Word
    instructions.
    
    V2: Now implemented using deposit (per Richard Henderson's comment)
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  11. Add Power7 VSX Logical Instructions

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX logical instructions that are defined
    by the Version 2.06 Power ISA (aka Power7):
    
       - xxland
       - xxlandc
       - xxlor
       - xxlxor
       - xxlnor
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  12. Add VSX Vector Move Instructions

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the vector move instructions:
    
      - xvabsdp - Vector Absolute Value Double-Precision
      - xvnabsdp - Vector Negative Absolute Value Double-Precision
      - xvnegdp - Vector Negate Double-Precision
      - xvcpsgndp - Vector Copy Sign Double-Precision
      - xvabssp - Vector Absolute Value Single-Precision
      - xvnabssp - Vector Negative Absolute Value Single-Precision
      - xvnegsp - Vector Negate Single-Precision
      - xvcpsgnsp - Vector Copy Sign Single-Precision
    
    V3: Per Paolo Bonzini's suggestion, used a temporary for the
    sign mask and andc.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  13. Add VSX Scalar Move Instructions

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the VSX scalar move instructions:
    
      - xsabsdp (Scalar Absolute Value Double-Precision)
      - xsnabspd (Scalar Negative Absolute Value Double-Precision)
      - xsnegdp (Scalar Negate Double-Precision)
      - xscpsgndp (Scalar Copy Sign Double-Precision)
    
    A common generator macro (VSX_SCALAR_MOVE) is added since these
    instructions vary only slightly from each other.
    
    Macros to support VSX XX2 and XX3 form opcodes are also added.
    These macros handle the overloading of "opcode 2" space (instruction
    bits 26:30) caused by AX and BX bits (29 and 30, respectively).
    
    V3: Per feedback from Paolo Bonzini, moved the sign mask into a
    temporary and used andc.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  14. roms: Flush icache when writing roms to guest memory

    agraf committed Dec 11, 2013
    We use the rom infrastructure to write firmware and/or initial kernel
    blobs into guest address space. So we're basically emulating the cache
    off phase on very early system bootup.
    
    That phase is usually responsible for clearing the instruction cache for
    anything it writes into cachable memory, to ensure that after reboot we
    don't happen to execute stale bits from the instruction cache.
    
    So we need to invalidate the icache every time we write a rom into guest
    address space. We do not need to do this for every DMA since the guest
    expects it has to flush the icache manually in that case.
    
    This fixes random reboot issues on e5500 (booke ppc) for me.
    
    Signed-off-by: Alexander Graf <agraf@suse.de>
  15. spapr: tie spapr-nvram to -pflash

    bonzini authored and agraf committed Nov 22, 2013
    spapr-nvram's drive property is currently connected to a non-existent
    "-machine nvram=<drivename>" option.  Instead, tie it to -pflash like
    other non-volatile RAM devices.  This provides the following possibilities
    for adding a backend for the sPAPR non-volatile RAM:
    
    * -pflash filename
    
    * -drive if=pflash,file=filename,format=raw,...
    
    * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo
    
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  16. PPC: Use default pci bus name for grackle and heathrow

    agraf committed Dec 4, 2013
    There's no good reason to call our bus "pci" rather than let the default
    bus name take over ("pci.0").
    
    The big downside to calling it different from anyone else is that tools
    that pass -device get confused. They are looking for a bus "pci.0" rather
    than "pci".
    
    To make life easier for everyone, let's just drop the name override.
    
    Signed-off-by: Alexander Graf <agraf@suse.de>
  17. spapr-rtas: add ibm, (get|set)-system-parameter

    aik authored and agraf committed Nov 19, 2013
    This adds very basic handlers for ibm,get-system-parameter and
    ibm,set-system-parameter RTAS calls.
    
    The only parameter handled at the moment is
    "platform-processor-diagnostics-run-mode" which is always disabled and
    does not support changing. This is expected to make
    "ppc64_cpu --run-mode=1" happy.
    
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    [agraf: s/papameter/parameter/g]
    Signed-off-by: Alexander Graf <agraf@suse.de>
  18. spapr-rtas: replace return code constants with macros

    aik authored and agraf committed Nov 19, 2013
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  19. target-ppc: move POWER7+ to a separate family

    aik authored and agraf committed Nov 19, 2013
    So far POWER7+ was a part of POWER7 family. However it has a different
    PVR base value so in order to support PVR masks, it needs a separate
    family class.
    
    This adds a new family class, PVR base and mask values and moves
    Power7+ v2.1 CPU to a new family. The class init function is copied
    from the POWER7 family.
    
    This defines a firmware name for the new family as "PowerPC,POWER7+"
    instead of previously used "PowerPC,POWER7" from the POWER7 family.
    The reason for that is that the Sapphire firmware (a h0st firmware)
    uses "PowerPC,POWER7+" already and since no specification defines
    exactly the CPU nodes naming in the device tree, we better stay
    in sync with the host firmware.
    
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  20. Add stxvw4x

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
    instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  21. Add stxsdx

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
    instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  22. Add lxvw4x

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
    instruction.
    
    V2: changed to use deposit_i64 per Richard Henderson's review.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  23. Add lxvdsx

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the Load VSX Vector Doubleword & Splat Indexed
    (lxvdsx) instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  24. Add lxsdx

    Tom Musta authored and agraf committed Nov 1, 2013
    This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
    instruction.
    
    The lower 8 bytes of the target register are undefined; this
    implementation leaves those bytes unaltered.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  25. Add xxpermdi

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds the xxpermdi instruction.  The instruction
    uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
    and BX).  This results in overloading of the opcode table
    with aliases, which can be seen in the GEN_XX3FORM_DM
    macro.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  26. Add stxvd2x

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds the stxvd2x instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  27. Add lxvd2x

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds the lxvd2x instruction.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  28. Add VSR to Global Registers

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds VSX VSRs to the the list of global register indices.
    More specifically, it adds the lower halves of the first 32 VSRs to
    the list of global register indices.  The upper halves of the first
    32 VSRs are already defined via cpu_fpr[].  And the second 32 VSRs
    are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  29. Add VSX Instruction Decoders

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds decoders for the VSX fields XT, XS, XA, XB and
    DM.  The first four are split fields and a general helper for
    these types of fields is also added.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  30. Add MSR VSX and Associated Exception

    Tom Musta authored and agraf committed Oct 22, 2013
    This patch adds support for the VSX bit of the PowerPC Machine
    State Register (MSR) as well as the corresponding VSX Unavailable
    exception.
    
    The VSX bit is added to the defined bits masks of the Power7 and
    Power8 CPU models.
    
    Signed-off-by: Tom Musta <tommusta@gmail.com>
    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Alexander Graf <agraf@suse.de>