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Commits on Dec 24, 2013
  1. target-rl78: Implement CMPW AX,#word

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  2. target-rl78: Implement SHRW AX,cnt

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  3. target-rl78: Prepare 4th MAP

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  4. target-rl78: Implement MOVW rp,#word

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  5. target-rl78: Reset GPR area

    authored
    This is not in the manual, but all registers in CPUState are cleared
    implicitly.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  6. target-rl78: Dump GPR banks

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  7. target-rl78: Implement SEL RB0..3

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  8. target-rl78: Prepare PSW

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  9. target-rl78: Prepare 2nd MAP

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  10. target-rl78: Implement MOV ES,#byte

    authored
    Introduce ES and CS.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  11. target-rl78: Prepare SP

    authored
    Prepare TCG variable and add to info output.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  12. target-rl78: Implement MOVW sfrp,#word

    authored
    This is the first instruction of GCC-generated _start, thus starting to
    make target-rl78 "usable".
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  13. rl78: Add MemoryRegion for GPRs

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  14. rl78: Add SFR MemoryRegion

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  15. target-rl78: Implement MOV !addr16,#byte

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  16. target-rl78: Load reset vector to PC

    authored
    Inspired by ARM M profile. Thanks to Peter for suggesting.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  17. rl78: Defer CPU realization til after BIOS is loaded

    authored
    On reset the CPU needs to load PC from memory.
    Therefore inline cpu_rl78_init() into machine init.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  18. target-rl78: Update PC

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  19. target-rl78: Add call to tcg_gen_debug_insn_start()

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  20. target-rl78: Add calls to gen_io_{start,end}()

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  21. target-rl78: Implement tlb_fill()

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  22. target-rl78: Implement CPU reset

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  23. target-rl78: Flesh out disas

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  24. rl78: Load BIOS

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  25. target-rl78: Add ELF machine identifier

    authored
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  26. rl78: Prepare Renesas RL78/G13 Promotion Board

    authored
    Set up RAM and code flash.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
  27. target-rl78: Add initial stubs for RL78

    authored
    Add support for {78k0,rl78}-softmmu in configure.
    Stub out target-78k0/, hw/78k0/ and hw/rl78/.
    
    Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Commits on Dec 22, 2013
  1. @agraf @aurel32

    PPC: Fix compilation with TCG debug

    agraf authored aurel32 committed
    The recent VSX patches broken compilation of QEMU when configurated
    with --enable-debug, as it was treating "target long" TCG variables
    as "i64" which is not true for 32bit targets.
    
    This patch fixes all the places that the compiler has found to use
    the correct variable type and if necessary manually cast.
    
    Reported-by: Stefan Weil <sw@weilnetz.de>
    Signed-off-by: Alexander Graf <agraf@suse.de>
    Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Commits on Dec 21, 2013
  1. @aurel32

    Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu

    aurel32 authored
    Patch queue for s390 - 2013-12-18
    
    This covers mostly minor bug fixes and implements the SIGP START
    hypercall which allows to start a remote CPU without changing its
    state.
    
    Cornelia Huck (1):
          s390x/kvm: Fix diagnose handling.
    
    Thomas Huth (7):
          s390x/kvm: Removed duplicated SIGP defines
          s390x/kvm: Removed s390_store_status stub
          s390x/kvm: Fix coding style in handle_sigp()
          s390x/kvm: Implemented SIGP START
          s390x/kvm: Simplified the calculation of the SIGP order code
          s390x/kvm: Fixed condition code for unknown SIGP orders
          s390x/ioinst: CHSC has to set a condition code
    
    * tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu:
      s390x/ioinst: CHSC has to set a condition code
      s390x/kvm: Fixed condition code for unknown SIGP orders
      s390x/kvm: Simplified the calculation of the SIGP order code
      s390x/kvm: Implemented SIGP START
      s390x/kvm: Fix coding style in handle_sigp()
      s390x/kvm: Removed s390_store_status stub
      s390x/kvm: Removed duplicated SIGP defines
      s390x/kvm: Fix diagnose handling.
  2. @aurel32

    target-sh4: Use new qemu_ld/st opcodes

    aurel32 authored
    Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  3. @aurel32

    target-mips: Use new qemu_ld/st opcodes

    aurel32 authored
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  4. @aurel32

    tcg/i386: fix a comment

    aurel32 authored
    The comments apply to 8-bit stores, not 8-byte stores.
    
    Reviewed-by: Richard Henderson <rth@twiddle.net>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Commits on Dec 20, 2013
  1. Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' int…

    Anthony Liguori authored
    …o staging
    
    Patch queue for ppc - 2013-12-20
    
    Alexander Graf (3):
          PPC: Use default pci bus name for grackle and heathrow
          roms: Flush icache when writing roms to guest memory
          PPC: Add VSX to hflags
    
    Alexey Kardashevskiy (5):
          powerpc: add PVR mask support
          target-ppc: move POWER7+ to a separate family
          spapr-rtas: replace return code constants with macros
          spapr-rtas: add ibm, (get|set)-system-parameter
          spapr: make sure RMA is in first mode of first memory node
    
    Greg Kurz (1):
          target-ppc: add stubs for KVM breakpoints
    
    Paolo Bonzini (1):
          spapr: tie spapr-nvram to -pflash
    
    Paul Mackerras (1):
          spapr: limit numa memory regions by ram size
    
    Peter Crosthwaite (2):
          device_tree: s/qemu_devtree/qemu_fdt globally
          device_tree: qemu_fdt_setprop: Rename val_array arg
    
    Tom Musta (19):
          Declare and Enable VSX
          Add MSR VSX and Associated Exception
          Add VSX Instruction Decoders
          Add VSR to Global Registers
          Add lxvd2x
          Add stxvd2x
          Add xxpermdi
          Add lxsdx
          Add lxvdsx
          Add lxvw4x
          Add stxsdx
          Add stxvw4x
          Add VSX Scalar Move Instructions
          Add VSX Vector Move Instructions
          Add Power7 VSX Logical Instructions
          Add xxmrgh/xxmrgl
          Add xxsel
          Add xxspltw
          Add xxsldwi
    
    * agraf/tags/signed-ppc-for-upstream: (32 commits)
      spapr: limit numa memory regions by ram size
      spapr: make sure RMA is in first mode of first memory node
      device_tree: qemu_fdt_setprop: Rename val_array arg
      device_tree: s/qemu_devtree/qemu_fdt globally
      PPC: Add VSX to hflags
      Add xxsldwi
      Add xxspltw
      Add xxsel
      Add xxmrgh/xxmrgl
      Add Power7 VSX Logical Instructions
      Add VSX Vector Move Instructions
      Add VSX Scalar Move Instructions
      roms: Flush icache when writing roms to guest memory
      spapr: tie spapr-nvram to -pflash
      PPC: Use default pci bus name for grackle and heathrow
      spapr-rtas: add ibm, (get|set)-system-parameter
      spapr-rtas: replace return code constants with macros
      target-ppc: move POWER7+ to a separate family
      Add stxvw4x
      Add stxsdx
      ...
  2. @paulusmack @agraf

    spapr: limit numa memory regions by ram size

    paulusmack authored agraf committed
    This makes sure that all NUMA memory blocks reside within RAM or
    have zero length.
    
    Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
  3. @aik @agraf

    spapr: make sure RMA is in first mode of first memory node

    aik authored agraf committed
    The SPAPR specification says that the RMA starts at the LPAR's logical
    address 0 and is the first logical memory block reported in
    the LPAR’s device tree.
    
    So SLOF only maps the first block and that block needs to span
    the full RMA.
    
    This makes sure that the RMA area is where SLOF expects it.
    
    Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
    Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
    Signed-off-by: Alexander Graf <agraf@suse.de>
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