* When access an uninitialized address, the vsim simulator will set the data bus to z+ or x+, but by no means certain. I suspect it is a bug. genrw.pl++, sal++.
* The time intervals of adjacent unit tests should not interleaved, even share the same endpoint. genrw.pl++, sal++.
* Pitfall in ram.v.tt: According to Verilog-1995, 'z' will extend to 64-bit as "00000000zzzzzzzz", which is now considered as a bug in Verilog-2001. I added some conditional test code to the template, so that when word_size > 32 the signals will be assigned the correct /^z+$/ values. Thanks to Sal's 64-bit test suit! sal++!