The MMU in Salent is reponsible for slicing "words" to "bytes". It bridges the gap between the processor and RAM. The RAM operates in words, but processor usually wants to access one single byte, two successive bytes, or a whole word.
MMU will play such a role that from the viewpoint of the processor, the memory is byte-addressable, and it is only word-addressable from the viewpoint of RAM.
The I/O ports for the MMU can be divided into two separate sub-interface, one for the processor, and one for RAM:
RAM <=> MMU <=> Processor
The sub-interface of MMU for RAM is exactly the same as the interface of RAM. MMU should take the full reponsibility to interact with RAM, including setting data bus, address bus, rw and strb control signals.
* bus_strb - out - Strobe signal issued by MMU itself to start the RAM.
* bus_rw - out - Read or write signal issued by MMU
* bus_data - inout
* bus_addr - out
* bus_mfc - in
The sub-interface of MMU for processor is very simple, consisting of only four signals:
* mar - in, reg - Memory Address Register storing the address of the leading byte
* byte - inout, reg - Memory Data Register storing the byte accessed or written by processor
* strb - in - Strobe signal issued by procssor to start the MMU.
* rw - in - Read/Write'
* mfc - out
It is critical to be aware of the fact that Salent's memory is little-endian. So the order of bytes in the memory is simalar to: