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backends
Update README
May 20, 2015 19:52
frontends
Ignore celldefine directive in verilog front-end
March 25, 2015 19:46
kernel
Added back-end auto-detect for .edif and .json
April 9, 2015 15:37
libs
Improved performance in equiv_simple
February 1, 2015 22:50
manual
Update APPNOTE_012_Verilog_to_BTOR.tex
April 29, 2015 12:58
misc
Hotfix for yosysjs/demo03.html
February 21, 2015 14:31
passes
Added "splice -wires"
April 13, 2015 19:28
techlibs
Improved xilinx "bram1" test
April 9, 2015 17:12
tests
Added "pmuxtree" command
April 7, 2015 20:27
.gitignore
More YosysJS stuff
February 16, 2015 13:23
CHANGELOG
Added new APIs to changelog
February 8, 2015 21:14
CodingReadme
CodingReadme
February 17, 2015 13:01
Makefile
Updated ABC to 51705b168d7a
April 4, 2015 11:47
README
Added support for initialized xilinx brams
April 6, 2015 17:07