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FPGA referrence implementation for aion equihash 2109
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earlmai Adding in primitive miner in Python
- Hardware guys should not write python
- Need to rewrite Stratum responses for Aion
- Need to add difficulty & job sumission
Latest commit 49cfaf3 Aug 2, 2018
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doc Updating with wiki assets Aug 1, 2018
.gitignore Initial Commit Jul 31, 2018


Algorithm: equihash (210,9)

Language: Verilog


src/rtl : Verilog of the design

src/build : Makefile to build design simulation

src/tb : Simple testbenches for design's major blocks

src/fpga : FPGA build files

doc/arch : Architecture related documentation

doc/test : Testbench & Simulation related documentation

Referenced Code:

  • Used for non pipelined blake2b with fixes for multimessage

  • Used for UART RTL
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