{"payload":{"header_redesign_enabled":false,"results":[{"id":"329668444","archived":false,"color":"#b2b7f8","followers":17,"has_funding_file":false,"hl_name":"ajackevic/ELEC5882","hl_trunc_description":"The Design and Implementation of a Pulse Compression Filter on an FPGA.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":329668444,"name":"ELEC5882","owner_id":57046549,"owner_login":"ajackevic","updated_at":"2021-08-07T10:45:04.045Z","has_issues":true}},"sponsorable":false,"topics":["fpga","matlab","fir","hilbert-transform","matched-filter","pulse-compression-filter","alpha-max-plus-beta-min","complex-fir","non-resoting-sqare-root"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":71,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aajackevic%252FELEC5882%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ajackevic/ELEC5882/star":{"post":"NWIjPQNigL9xIqRsxY8M53ghwvNNQj0Ai-ss4vvzI-Km_5qQrEWLBihzCq2TKMIys2BQOfwvfM7HPL1bhAeQGw"},"/ajackevic/ELEC5882/unstar":{"post":"w2GyOgV0n0ZHc1WplY3SPsgxvbZ3dY9biti3uajXMrQLEx7c_j_fQ8s_PxEZK5_G5RI2LR-e-uT6n3u26eTERg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"CLECZUi0eMyHBgRVADGG_5HZbb0RVLOe8xtXcgXQefezd0NLcM-PkE5M6RhgtNd4KVVWP9D7ORTiWSNdyT8isQ"}}},"title":"Repository search results"}