MCVerilog

Our BoilerMake 2014 project

What?

MCVerilog is a Verilog to Minecraft compiler. Given a source file conforming to a subset of the Verilog syntax, the project generates a Minecraft world containing a redstone circuit that models the hardware described by the source file.

Why?

A better question is, why not?

If you need a better answer than that, then you're not really the target audience of this project.

While taking Computer Architecture at UIUC and Ball State, our team was inspired to use Verilog HDL to generate redstone circuits in Minecraft. Verilog is a hardware description language that describes how electrical components are wired; our project parses Verilog source files to build equivalent circuits within Minecraft.

We're most proud of the many potential uses for this project. Imagine writing a processor in Verilog and running it through a compiler and having a working redstone circuit, rather than spending countless hours building it manually in Minecraft. Our project will greatly accelerate development of amazing Minecraft projects.

How?

• Java
• MCModify - modified to work in our project
• 36 sleepless hours at BoilerMake
• Magic

Who?

• Alex Cordonnier, UIUC
• Brandon Chong, UIUC
• Brandon Groff, Ball State
• Daniel Carballal, UIUC