semester project for cs 150 - components and design techniques for digital systems
Verilog C Other
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checkpoint three temproary addresses for important variables:
seconds passed:  0x1f0000b0 (set to ZERO upon init)
minutes passed:  0x1f0000b4 (set to ZERO upon init)
byte to send:    0x1f0000b8 (used as a temp global in print_time isr)
total seconds:   0x1f0000bc (set to ZERO upon init)
state:           0x1f0000c0 (CLEAR upon init)
SW_RTC:          0x1f0000c4 (set to ZERO upon init)
timer_print_bit: 0x1f0000c8 (set to ONE upon init)
inIdx:           0x1f0000d0 (set to ZERO upon init)
outIdx:          0x1f0000d4 (set to ZERO upon init)
buffer:          0x1f0000d8
dec seconds lsb: 	 0x1f0000a0
dec seconds msb: 	 0x1f0000a4
seconds diff:		 0x1f0000a8
count:			 0x1f0000ac

start program: 0x10005000

Frame 1: 0x1040_0000
Frame 2: 0x1080_0000
mem_mapped GP regs
GP_frame_reg: 80000040
GP_code_reg:  80000030
frame_count:  80000050 (if even, frame is 1040)

store GP insts: 0x1001_0000

spec broken down:
isr resides in start.s (isr folder) 

timer isr: 
add 1 second to compare register (50M cycles)
add 1 second to seconds passed global value
if == 60, set to 0, increment minutes passed
if timer_print_bit is set:
	call C print function (may be assembly if we decide) (no arguments) to fill the FIFO
	jump to UARTTX

increment every time count overflows

UARTRX_isr: (done in assembly in start.s)
receive from UART, store to STATE
case (state)
	e: set timer_print_bit (global var)
	d: clear timer_print_bit
	else stores into STATE (used by application code)

>? if FIFO empty (inIdx == outIdx) jump to done
otherwise dequeue from fifo (only if DataInReady is high)
if outIdx == buffer size, outIdx = 0