The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
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README.md

Description

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

Features

  • CISC processor with microcode,
  • WISHBONE revision B.3 compatible MASTER interface,
  • Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
  • Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
  • Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (Processor verification). The result of execution was compared,
  • Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
  • Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification is automatically extracted from the Doxygen HTML output.

License

The OpenCores ao68000 IP Core is licensed under the Simplified BSD License. Works based on this project may be released under a proprietary license or as closed source software.

WISHBONE compatibility

  • Version: WISHBONE specification Revision B.3,
  • General description: 32-bit WISHBONE Master interface,
  • WISHBONE signals described in IO Ports,
  • Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,
  • Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt,
  • Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector,
  • WISHBONE data port size: 32-bit,
  • Data port granularity: 8-bits,
  • Data port maximum operand size: 32-bits,
  • Data transfer ordering: BIG ENDIAN,
  • Data transfer sequencing: UNDEFINED,
  • Constraints on CLK_I signal: described in Clocks, maximum frequency: about 82 MHz.

Use

  • The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC (http://opencores.org/project,aoocs)
  • It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to init program lookup (System-on-Chip example with ao68000 running Linux).

Similar projects

Other free soft-core implementations of M68000 microprocessor include:

Limitations

  • Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
  • TRACE not tested,
  • The core is still large compared to other implementations.

TODO

  • Optimize the desgin and microcode,
  • Count the exact cycle count for every instruction,
  • Test TRACE,
  • Write more documentation.

Status

  • April 2010: Tested with WinUAE software MC68000 emulator,
  • April 2010: Booted Linux kernel up to init process lookup,
  • December 2010: Runs as a processor in OpenCores aoOCS project,
  • January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
  • July 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.

Requirements

  • Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the tb_ao68000 testbench/wrapper,
  • Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the tb_ao68000 testbench/wrapper,
  • GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
  • Java runtime (http://java.sun.com) is required to run the ao68000_tool (ao68000_tool documentation),
  • Java SDK (http://java.sun.com) is required to compile the ao68000_tool (ao68000_tool documentation),
  • Altera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the soc_for_linux System-on-Chip (System-on-Chip example with ao68000 running Linux).

Glossary

  • ao68000 - the ao68000 IP Core processor,
  • MC68000 - the original Motorola MC68000 processor.

Structure diagram

Structure diagram