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Add mem(64,128)to(128,64) fifo + hierachy for _wrappers

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commit 0db6acb80805702aac3dd3e269291192e79f3460 1 parent 7798c8f
@alown authored
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152 xc6/src/datawrapper.vhd
@@ -14,6 +14,14 @@ use ieee.std_logic_1164.all;
---------------------------------------------------------------------------
entity datawrapper is
---------------------------------------------------------------------------
+generic
+(
+ NUM_DQ_PINS : integer := 16;
+ MASK_SIZE : integer := 16;
+ MEM_ADDR_WIDTH : integer := 14;
+ MEM_BANKADDR_WIDTH : integer := 3;
+ DATA_PORT_SIZE : integer := 128
+);
port
(
sys_rst : in std_logic;
@@ -32,30 +40,26 @@ port
adc_datard_wr_count : in std_logic_vector(14 downto 0);
--DDR interface
- c3_p0_cmd_clk : out std_logic;
- c3_p0_cmd_en : out std_logic;
- c3_p0_cmd_instr : out std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : out std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : out std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : in std_logic;
- c3_p0_cmd_full : in std_logic;
- c3_p0_wr_clk : out std_logic;
- c3_p0_wr_en : out std_logic;
- c3_p0_wr_mask : out std_logic_vector(15 downto 0);
- c3_p0_wr_data : out std_logic_vector(127 downto 0);
- c3_p0_wr_full : in std_logic;
- c3_p0_wr_empty : in std_logic;
- c3_p0_wr_count : in std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : in std_logic;
- c3_p0_wr_error : in std_logic;
- c3_p0_rd_clk : out std_logic;
- c3_p0_rd_en : out std_logic;
- c3_p0_rd_data : in std_logic_vector(127 downto 0);
- c3_p0_rd_full : in std_logic;
- c3_p0_rd_empty : in std_logic;
- c3_p0_rd_count : in std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : in std_logic;
- c3_p0_rd_error : in std_logic;
+ ddrclk : in std_logic;
+ mcb3_dram_dq : inout std_logic_vector(NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_odt : out std_logic;
+ mcb3_dram_reset_n : out std_logic;
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs_p : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_dqs_p : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck_p : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
--FX3 interface
fx3_adcdata : out std_logic_vector(63 downto 0);
@@ -119,9 +123,60 @@ architecture Behavioral of datawrapper is
);
end component DCM_SP;
+ component memwrapper
+ generic (
+ NUM_DQ_PINS : integer := 16;
+ MASK_SIZE : integer := 16;
+ MEM_ADDR_WIDTH : integer := 14;
+ MEM_BANKADDR_WIDTH : integer := 3;
+ DATA_PORT_SIZE : integer := 128
+ );
+ port (
+ sys_rst : in std_logic;
+ clk : in std_logic;
+
+ --MCB interface
+ ddrclk : in std_logic;
+ mcb3_dram_dq : inout std_logic_vector(NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_odt : out std_logic;
+ mcb3_dram_reset_n : out std_logic;
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs_p : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_dqs_p : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck_p : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
+
+ --ADC FIFO interface
+ adc_wr_clk : in std_logic;
+ adc_wr_en : in std_logic;
+ adc_wr_data : in std_logic_vector(63 downto 0);
+ adc_wr_full : out std_logic;
+
+ adc_rd_clk : in std_logic;
+ adc_rd_en : in std_logic;
+ adc_rd_data : out std_logic_vector(63 downto 0);
+ adc_rd_empty : out std_logic
+ );
+ end component memwrapper;
+
signal dcm_fb : std_logic;
signal slowclk : std_logic;
+ signal mem_adc_wr_en, mem_adc_rd_en : std_logic;
+ signal mem_adc_wr_data, mem_adc_rd_data : std_logic_vector(63 downto 0);
+ signal mem_adc_wr_full, mem_adc_rd_empty : std_logic;
+
type state_type is (st0_direct, st1_save, st2_restore);
signal state : state_type := st0_direct;
@@ -162,7 +217,7 @@ begin
PSDONE => open,
STATUS => open,
CLKFB => dcm_fb,
- CLKIN => fsmclk,
+ CLKIN => clk,
DSSEN => open,
PSCLK => open,
PSEN => open,
@@ -170,13 +225,46 @@ begin
RST => sys_rst
);
- --Tie pins low as required by ug388 pg. 51
- c3_p0_cmd_byte_addr(3 downto 0) <= "0000";
-
- --No need for 3 different clocks!
- c3_p0_cmd_clk <= clk;
- c3_p0_wr_clk <= clk;
- c3_p0_rd_clk <= clk;
+ Inst_memwrapper : memwrapper
+ generic map (
+ NUM_DQ_PINS => NUM_DQ_PINS,
+ MASK_SIZE => MASK_SIZE,
+ MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
+ MEM_BANKADDR_WIDTH => MEM_BANKADDR_WIDTH,
+ DATA_PORT_SIZE => DATA_PORT_SIZE
+ )
+ port map (
+ sys_rst => sys_rst,
+ clk => clk,
+ ddrclk => ddrclk,
+ mcb3_dram_dq => mcb3_dram_dq,
+ mcb3_dram_a => mcb3_dram_a,
+ mcb3_dram_ba => mcb3_dram_ba,
+ mcb3_dram_ras_n => mcb3_dram_ras_n,
+ mcb3_dram_cas_n => mcb3_dram_cas_n,
+ mcb3_dram_we_n => mcb3_dram_we_n,
+ mcb3_dram_odt => mcb3_dram_odt,
+ mcb3_dram_reset_n => mcb3_dram_reset_n,
+ mcb3_dram_cke => mcb3_dram_cke,
+ mcb3_dram_dm => mcb3_dram_dm,
+ mcb3_dram_udqs_p => mcb3_dram_udqs_p,
+ mcb3_dram_udqs_n => mcb3_dram_udqs_n,
+ mcb3_rzq => mcb3_rzq,
+ mcb3_zio => mcb3_zio,
+ mcb3_dram_udm => mcb3_dram_udm,
+ mcb3_dram_dqs_p => mcb3_dram_dqs_p,
+ mcb3_dram_dqs_n => mcb3_dram_dqs_n,
+ mcb3_dram_ck_p => mcb3_dram_ck_p,
+ mcb3_dram_ck_n => mcb3_dram_ck_n,
+ adc_wr_clk => clk,
+ adc_wr_en => mem_adc_wr_en,
+ adc_wr_data => mem_adc_wr_data,
+ adc_wr_full => mem_adc_wr_full,
+ adc_rd_clk => clk,
+ adc_rd_en => mem_adc_rd_en,
+ adc_rd_data => mem_adc_rd_data,
+ adc_rd_empty => mem_adc_rd_empty
+ );
cfg <= (others => 'Z');
View
282 xc6/src/main.vhd
@@ -207,86 +207,6 @@ architecture Behavioral of main is
);
end component clockbuf;
- component ddr3mem
- generic (
- C3_P0_MASK_SIZE : integer := 16;
- C3_P0_DATA_PORT_SIZE : integer := 128;
- C3_MEMCLK_PERIOD : integer := 2500;
- -- Memory data transfer clock period.
- C3_RST_ACT_LOW : integer := 0;
- -- # = 1 for active low reset,
- -- # = 0 for active high reset.
- C3_CALIB_SOFT_IP : string := "TRUE";
- -- # = TRUE, Enables the soft calibration logic,
- -- # = FALSE, Disables the soft calibration logic.
- C3_SIMULATION : string := "FALSE";
- -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
- -- # = FALSE, Implementing the design.
- DEBUG_EN : integer := 1;
- -- # = 1, Enable debug signals/controls,
- -- = 0, Disable debug signals/controls.
- C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
- -- The order in which user address is provided to the memory controller,
- -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
- C3_NUM_DQ_PINS : integer := 16;
- -- External memory data width.
- C3_MEM_ADDR_WIDTH : integer := 14;
- -- External memory address width.
- C3_MEM_BANKADDR_WIDTH : integer := 3
- -- External memory bank address width.
- );
- port (
- mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
- mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
- mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
- mcb3_dram_ras_n : out std_logic;
- mcb3_dram_cas_n : out std_logic;
- mcb3_dram_we_n : out std_logic;
- mcb3_dram_odt : out std_logic;
- mcb3_dram_reset_n : out std_logic;
- mcb3_dram_cke : out std_logic;
- mcb3_dram_dm : out std_logic;
- mcb3_dram_udqs : inout std_logic;
- mcb3_dram_udqs_n : inout std_logic;
- mcb3_rzq : inout std_logic;
- mcb3_zio : inout std_logic;
- mcb3_dram_udm : out std_logic;
- c3_sys_clk : in std_logic;
- c3_sys_rst_i : in std_logic;
- c3_calib_done : out std_logic;
- c3_clk0 : out std_logic;
- c3_rst0 : out std_logic;
- mcb3_dram_dqs : inout std_logic;
- mcb3_dram_dqs_n : inout std_logic;
- mcb3_dram_ck : out std_logic;
- mcb3_dram_ck_n : out std_logic;
- c3_p0_cmd_clk : in std_logic;
- c3_p0_cmd_en : in std_logic;
- c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : out std_logic;
- c3_p0_cmd_full : out std_logic;
- c3_p0_wr_clk : in std_logic;
- c3_p0_wr_en : in std_logic;
- c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
- c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_wr_full : out std_logic;
- c3_p0_wr_empty : out std_logic;
- c3_p0_wr_count : out std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : out std_logic;
- c3_p0_wr_error : out std_logic;
- c3_p0_rd_clk : in std_logic;
- c3_p0_rd_en : in std_logic;
- c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_rd_full : out std_logic;
- c3_p0_rd_empty : out std_logic;
- c3_p0_rd_count : out std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : out std_logic;
- c3_p0_rd_error : out std_logic
- );
- end component ddr3mem;
-
component fx3
port (
sys_rst : in std_logic;
@@ -367,6 +287,13 @@ architecture Behavioral of main is
end component think;
component datawrapper
+ generic (
+ NUM_DQ_PINS : integer := 16;
+ MASK_SIZE : integer := 16;
+ MEM_ADDR_WIDTH : integer := 14;
+ MEM_BANKADDR_WIDTH : integer := 3;
+ DATA_PORT_SIZE : integer := 128
+ );
port (
sys_rst : in std_logic;
clk : in std_logic;
@@ -384,30 +311,26 @@ architecture Behavioral of main is
adc_datard_wr_count : in std_logic_vector(14 downto 0);
--DDR interface
- c3_p0_cmd_clk : out std_logic;
- c3_p0_cmd_en : out std_logic;
- c3_p0_cmd_instr : out std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : out std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : out std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : in std_logic;
- c3_p0_cmd_full : in std_logic;
- c3_p0_wr_clk : out std_logic;
- c3_p0_wr_en : out std_logic;
- c3_p0_wr_mask : out std_logic_vector(15 downto 0);
- c3_p0_wr_data : out std_logic_vector(127 downto 0);
- c3_p0_wr_full : in std_logic;
- c3_p0_wr_empty : in std_logic;
- c3_p0_wr_count : in std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : in std_logic;
- c3_p0_wr_error : in std_logic;
- c3_p0_rd_clk : out std_logic;
- c3_p0_rd_en : out std_logic;
- c3_p0_rd_data : in std_logic_vector(127 downto 0);
- c3_p0_rd_full : in std_logic;
- c3_p0_rd_empty : in std_logic;
- c3_p0_rd_count : in std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : in std_logic;
- c3_p0_rd_error : in std_logic;
+ ddrclk : in std_logic;
+ mcb3_dram_dq : inout std_logic_vector(NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_odt : out std_logic;
+ mcb3_dram_reset_n : out std_logic;
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs_p : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_dqs_p : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck_p : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
--FX3 interface
fx3_adcdata : out std_logic_vector(63 downto 0);
@@ -433,34 +356,6 @@ architecture Behavioral of main is
signal fx3_adcdataclk : std_logic;
signal fx3_adcdataen : std_logic;
- signal c3_calib_done : std_logic;
- signal c3_clk0, c3_rst0 : std_logic;
- signal c3_p0_cmd_clk : std_logic;
- signal c3_p0_cmd_en : std_logic;
- signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p0_cmd_empty : std_logic;
- signal c3_p0_cmd_full : std_logic;
- signal c3_p0_wr_clk : std_logic;
- signal c3_p0_wr_en : std_logic;
- signal c3_p0_wr_full : std_logic;
- signal c3_p0_wr_empty : std_logic;
- signal c3_p0_wr_count : std_logic_vector(6 downto 0);
- signal c3_p0_wr_underrun : std_logic;
- signal c3_p0_wr_error : std_logic;
- signal c3_p0_rd_clk : std_logic;
- signal c3_p0_rd_en : std_logic;
- signal c3_p0_rd_full : std_logic;
- signal c3_p0_rd_empty : std_logic;
- signal c3_p0_rd_count : std_logic_vector(6 downto 0);
- signal c3_p0_rd_overflow : std_logic;
- signal c3_p0_rd_error : std_logic;
-
- signal c3_p0_wr_data : std_logic_vector(DATA_PORT_SIZE-1 downto 0);
- signal c3_p0_rd_data : std_logic_vector(DATA_PORT_SIZE-1 downto 0);
- signal c3_p0_wr_mask : std_logic_vector(MASK_SIZE-1 downto 0);
-
signal cfg_adc : std_logic_vector(4 downto 0);
signal cfg_datawrapper : std_logic_vector(4 downto 0);
signal cfg_input : std_logic_vector(4 downto 0);
@@ -526,75 +421,6 @@ begin
datard_wr_count => adc_datard_wr_count
);
- Inst_ddr3mem : ddr3mem
- generic map (
- C3_P0_MASK_SIZE => MASK_SIZE,
- C3_P0_DATA_PORT_SIZE => DATA_PORT_SIZE,
- C3_MEMCLK_PERIOD => 2500,
- C3_RST_ACT_LOW => 0,
- DEBUG_EN => 1,
- C3_CALIB_SOFT_IP => "TRUE",
- C3_SIMULATION => "FALSE",
- C3_MEM_ADDR_ORDER => "ROW_BANK_COLUMN",
- C3_NUM_DQ_PINS => NUM_DQ_PINS,
- C3_MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
- C3_MEM_BANKADDR_WIDTH => MEM_BANKADDR_WIDTH
- )
- port map (
- mcb3_dram_dq => mcb3_dram_dq,
- mcb3_dram_a => mcb3_dram_a,
- mcb3_dram_ba => mcb3_dram_ba,
- mcb3_dram_ras_n => mcb3_dram_ras_n,
- mcb3_dram_cas_n => mcb3_dram_cas_n,
- mcb3_dram_we_n => mcb3_dram_we_n,
- mcb3_dram_odt => mcb3_dram_odt,
- mcb3_dram_cke => mcb3_dram_cke,
- mcb3_dram_dm => mcb3_dram_dm,
- mcb3_rzq => mcb3_rzq,
- mcb3_zio => mcb3_zio,
- mcb3_dram_dqs => mcb3_dram_dqs_p,
- mcb3_dram_dqs_n => mcb3_dram_dqs_n,
- mcb3_dram_ck => mcb3_dram_ck_p,
- mcb3_dram_ck_n => mcb3_dram_ck_n,
- mcb3_dram_udqs => mcb3_dram_udqs_p,
- mcb3_dram_udqs_n => mcb3_dram_udqs_n,
- mcb3_dram_udm => mcb3_dram_udm,
- mcb3_dram_reset_n => mcb3_dram_reset_n,
-
- c3_sys_clk => ddrclk,
- c3_sys_rst_i => sys_rst,
- c3_calib_done => c3_calib_done,
- c3_clk0 => c3_clk0,
- c3_rst0 => c3_rst0,
-
- c3_p0_cmd_clk => c3_p0_cmd_clk,
- c3_p0_cmd_en => c3_p0_cmd_en,
- c3_p0_cmd_instr => c3_p0_cmd_instr,
- c3_p0_cmd_bl => c3_p0_cmd_bl,
- c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
- c3_p0_cmd_empty => c3_p0_cmd_empty,
- c3_p0_cmd_full => c3_p0_cmd_full,
-
- c3_p0_wr_clk => c3_p0_wr_clk,
- c3_p0_wr_en => c3_p0_wr_en,
- c3_p0_wr_mask => c3_p0_wr_mask,
- c3_p0_wr_data => c3_p0_wr_data,
- c3_p0_wr_full => c3_p0_wr_full,
- c3_p0_wr_empty => c3_p0_wr_empty,
- c3_p0_wr_count => c3_p0_wr_count,
- c3_p0_wr_underrun => c3_p0_wr_underrun,
- c3_p0_wr_error => c3_p0_wr_error,
-
- c3_p0_rd_clk => c3_p0_rd_clk,
- c3_p0_rd_en => c3_p0_rd_en,
- c3_p0_rd_data => c3_p0_rd_data,
- c3_p0_rd_full => c3_p0_rd_full,
- c3_p0_rd_empty => c3_p0_rd_empty,
- c3_p0_rd_count => c3_p0_rd_count,
- c3_p0_rd_overflow => c3_p0_rd_overflow,
- c3_p0_rd_error => c3_p0_rd_error
- );
-
Inst_fx3 : fx3
port map (
sys_rst => sys_rst,
@@ -652,10 +478,18 @@ begin
);
Inst_datawrapper : datawrapper
+ generic map (
+ NUM_DQ_PINS => NUM_DQ_PINS,
+ MASK_SIZE => MASK_SIZE,
+ MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
+ MEM_BANKADDR_WIDTH => MEM_BANKADDR_WIDTH,
+ DATA_PORT_SIZE => DATA_PORT_SIZE
+ )
port map (
sys_rst => sys_rst,
clk => fsmclk,
cfg => cfg_datawrapper,
+
adc_datard => adc_datard,
adc_datard_clk => adc_datard_clk,
adc_datard_en => adc_datard_en,
@@ -663,30 +497,28 @@ begin
adc_datard_empty => adc_datard_empty,
adc_datard_rd_count => adc_datard_rd_count,
adc_datard_wr_count => adc_datard_wr_count,
- c3_p0_cmd_clk => c3_p0_cmd_clk,
- c3_p0_cmd_en => c3_p0_cmd_en,
- c3_p0_cmd_instr => c3_p0_cmd_instr,
- c3_p0_cmd_bl => c3_p0_cmd_bl,
- c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
- c3_p0_cmd_empty => c3_p0_cmd_empty,
- c3_p0_cmd_full => c3_p0_cmd_full,
- c3_p0_wr_clk => c3_p0_wr_clk,
- c3_p0_wr_en => c3_p0_wr_en,
- c3_p0_wr_mask => c3_p0_wr_mask,
- c3_p0_wr_data => c3_p0_wr_data,
- c3_p0_wr_full => c3_p0_wr_full,
- c3_p0_wr_empty => c3_p0_wr_empty,
- c3_p0_wr_count => c3_p0_wr_count,
- c3_p0_wr_underrun => c3_p0_wr_underrun,
- c3_p0_wr_error => c3_p0_wr_error,
- c3_p0_rd_clk => c3_p0_rd_clk,
- c3_p0_rd_en => c3_p0_rd_en,
- c3_p0_rd_data => c3_p0_rd_data,
- c3_p0_rd_full => c3_p0_rd_full,
- c3_p0_rd_empty => c3_p0_rd_empty,
- c3_p0_rd_count => c3_p0_rd_count,
- c3_p0_rd_overflow => c3_p0_rd_overflow,
- c3_p0_rd_error => c3_p0_rd_error,
+
+ ddrclk => ddrclk,
+ mcb3_dram_dq => mcb3_dram_dq,
+ mcb3_dram_a => mcb3_dram_a,
+ mcb3_dram_ba => mcb3_dram_ba,
+ mcb3_dram_ras_n => mcb3_dram_ras_n,
+ mcb3_dram_cas_n => mcb3_dram_cas_n,
+ mcb3_dram_we_n => mcb3_dram_we_n,
+ mcb3_dram_odt => mcb3_dram_odt,
+ mcb3_dram_reset_n => mcb3_dram_reset_n,
+ mcb3_dram_cke => mcb3_dram_cke,
+ mcb3_dram_dm => mcb3_dram_dm,
+ mcb3_dram_udqs_p => mcb3_dram_udqs_p,
+ mcb3_dram_udqs_n => mcb3_dram_udqs_n,
+ mcb3_rzq => mcb3_rzq,
+ mcb3_zio => mcb3_zio,
+ mcb3_dram_udm => mcb3_dram_udm,
+ mcb3_dram_dqs_p => mcb3_dram_dqs_p,
+ mcb3_dram_dqs_n => mcb3_dram_dqs_n,
+ mcb3_dram_ck_p => mcb3_dram_ck_p,
+ mcb3_dram_ck_n => mcb3_dram_ck_n,
+
fx3_adcdata => fx3_adcdata,
fx3_adcdataclk => fx3_adcdataclk,
fx3_adcdataen => fx3_adcdataen
View
391 xc6/src/memwrapper.vhd
@@ -17,38 +17,40 @@ use unisim.vcomponents.all;
---------------------------------------------------------------------------
entity memwrapper is
---------------------------------------------------------------------------
+generic
+(
+ NUM_DQ_PINS : integer := 16;
+ MASK_SIZE : integer := 16;
+ MEM_ADDR_WIDTH : integer := 14;
+ MEM_BANKADDR_WIDTH : integer := 3;
+ DATA_PORT_SIZE : integer := 128
+);
port
(
sys_rst : in std_logic;
clk : in std_logic;
--MCB interface
- c3_p0_cmd_clk : out std_logic;
- c3_p0_cmd_en : out std_logic;
- c3_p0_cmd_instr : out std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : out std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : out std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : in std_logic;
- c3_p0_cmd_full : in std_logic;
-
- c3_p0_wr_clk : out std_logic;
- c3_p0_wr_en : out std_logic;
- c3_p0_wr_mask : out std_logic_vector(15 downto 0);
- c3_p0_wr_data : out std_logic_vector(127 downto 0);
- c3_p0_wr_full : in std_logic;
- c3_p0_wr_empty : in std_logic;
- c3_p0_wr_count : in std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : in std_logic;
- c3_p0_wr_error : in std_logic;
-
- c3_p0_rd_clk : out std_logic;
- c3_p0_rd_en : out std_logic;
- c3_p0_rd_data : in std_logic_vector(127 downto 0);
- c3_p0_rd_full : in std_logic;
- c3_p0_rd_empty : in std_logic;
- c3_p0_rd_count : in std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : in std_logic;
- c3_p0_rd_error : in std_logic;
+ ddrclk : in std_logic;
+ mcb3_dram_dq : inout std_logic_vector(NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_odt : out std_logic;
+ mcb3_dram_reset_n : out std_logic;
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs_p : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_dqs_p : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck_p : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
--ADC FIFO interface
adc_wr_clk : in std_logic;
@@ -59,8 +61,7 @@ port
adc_rd_clk : in std_logic;
adc_rd_en : in std_logic;
adc_rd_data : out std_logic_vector(63 downto 0);
- adc_rd_empty : out std_logic;
-
+ adc_rd_empty : out std_logic
);
end memwrapper;
@@ -69,72 +70,334 @@ end memwrapper;
architecture Behavioral of memwrapper is
---------------------------------------------------------------------------
- component memfifo
+ component ddr3mem
+ generic (
+ C3_P0_MASK_SIZE : integer := 16;
+ C3_P0_DATA_PORT_SIZE : integer := 128;
+ C3_MEMCLK_PERIOD : integer := 2500;
+ -- Memory data transfer clock period.
+ C3_RST_ACT_LOW : integer := 0;
+ -- # = 1 for active low reset,
+ -- # = 0 for active high reset.
+ C3_CALIB_SOFT_IP : string := "TRUE";
+ -- # = TRUE, Enables the soft calibration logic,
+ -- # = FALSE, Disables the soft calibration logic.
+ C3_SIMULATION : string := "FALSE";
+ -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
+ -- # = FALSE, Implementing the design.
+ DEBUG_EN : integer := 1;
+ -- # = 1, Enable debug signals/controls,
+ -- = 0, Disable debug signals/controls.
+ C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
+ -- The order in which user address is provided to the memory controller,
+ -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
+ C3_NUM_DQ_PINS : integer := 16;
+ -- External memory data width.
+ C3_MEM_ADDR_WIDTH : integer := 14;
+ -- External memory address width.
+ C3_MEM_BANKADDR_WIDTH : integer := 3
+ -- External memory bank address width.
+ );
+ port (
+ mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_odt : out std_logic;
+ mcb3_dram_reset_n : out std_logic;
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ c3_sys_clk : in std_logic;
+ c3_sys_rst_i : in std_logic;
+ c3_calib_done : out std_logic;
+ c3_clk0 : out std_logic;
+ c3_rst0 : out std_logic;
+ mcb3_dram_dqs : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
+ c3_p0_cmd_clk : in std_logic;
+ c3_p0_cmd_en : in std_logic;
+ c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p0_cmd_empty : out std_logic;
+ c3_p0_cmd_full : out std_logic;
+ c3_p0_wr_clk : in std_logic;
+ c3_p0_wr_en : in std_logic;
+ c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+ c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+ c3_p0_wr_full : out std_logic;
+ c3_p0_wr_empty : out std_logic;
+ c3_p0_wr_count : out std_logic_vector(6 downto 0);
+ c3_p0_wr_underrun : out std_logic;
+ c3_p0_wr_error : out std_logic;
+ c3_p0_rd_clk : in std_logic;
+ c3_p0_rd_en : in std_logic;
+ c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+ c3_p0_rd_full : out std_logic;
+ c3_p0_rd_empty : out std_logic;
+ c3_p0_rd_count : out std_logic_vector(6 downto 0);
+ c3_p0_rd_overflow : out std_logic;
+ c3_p0_rd_error : out std_logic
+ );
+ end component ddr3mem;
+
+ --64*256/128*128 sized
+ component mem64to128fifo
port (
- rst : in std_logic;
- wr_clk : in std_logic;
- rd_clk : in std_logic;
- din : in std_logic_vector(63 downto 0);
- wr_en : in std_logic;
- rd_en : in std_logic;
- dout : out std_logic_vector(127 downto 0);
- full : out std_logic;
- empty : out std_logic
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(63 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(127 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ rd_data_count : out std_logic_vector(7 downto 0);
+ wr_data_count : out std_logic_vector(8 downto 0)
);
- end component memfifo;
+ end component mem64to128fifo;
+
+ component mem128to64fifo
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(127 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(63 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ rd_data_count : out std_logic_vector(8 downto 0);
+ wr_data_count : out std_logic_vector(7 downto 0)
+ );
+ end component mem128to64fifo;
+
+ constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
+ constant CMD_READ : std_logic_vector(2 downto 0) := "001";
+ constant CMD_WRITE_AP : std_logic_vector(2 downto 0) := "010";
+ constant CMD_READ_AP : std_logic_vector(2 downto 0) := "011";
+ constant CMD_REFRESH : std_logic_vector(2 downto 0) := "100";
- signal adc_wrbuf_clk, adc_rdbuf_clk : std_logic;
- signal adc_wrbuf_en, adc_rdbuf_en : std_logic;
+ signal c3_calib_done : std_logic;
+ signal c3_clk0, c3_rst0 : std_logic;
+ signal c3_p0_cmd_clk : std_logic;
+ signal c3_p0_cmd_en : std_logic;
+ signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
+ signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
+ signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
+ signal c3_p0_cmd_empty : std_logic;
+ signal c3_p0_cmd_full : std_logic;
+ signal c3_p0_wr_clk : std_logic;
+ signal c3_p0_wr_en : std_logic;
+ signal c3_p0_wr_full : std_logic;
+ signal c3_p0_wr_empty : std_logic;
+ signal c3_p0_wr_count : std_logic_vector(6 downto 0);
+ signal c3_p0_wr_underrun : std_logic;
+ signal c3_p0_wr_error : std_logic;
+ signal c3_p0_rd_clk : std_logic;
+ signal c3_p0_rd_en : std_logic;
+ signal c3_p0_rd_full : std_logic;
+ signal c3_p0_rd_empty : std_logic;
+ signal c3_p0_rd_count : std_logic_vector(6 downto 0);
+ signal c3_p0_rd_overflow : std_logic;
+ signal c3_p0_rd_error : std_logic;
+
+ signal c3_p0_wr_data : std_logic_vector(DATA_PORT_SIZE-1 downto 0);
+ signal c3_p0_rd_data : std_logic_vector(DATA_PORT_SIZE-1 downto 0);
+ signal c3_p0_wr_mask : std_logic_vector(MASK_SIZE-1 downto 0);
+
+
+ signal adc_wrbuf_en, adc_rdbuf_en : std_logic := '0';
signal adc_wrbuf_data, adc_rdbuf_data : std_logic_vector(127 downto 0);
signal adc_wrbuf_full, adc_rdbuf_full : std_logic;
signal adc_wrbuf_empty, adc_rdbuf_empty : std_logic;
+ signal adc_wrbuf_wr_count, adc_rdbuf_wr_count : std_logic_vector(8 downto 0);
+ signal adc_wrbuf_rd_count, adc_rdbuf_rd_count : std_logic_vector(7 downto 0);
+
type state_type is (st0_default, st1_read, st1_write);
signal state : state_type := st0_default;
+ --Max location for a 2GBit/16bit wide module, appearing as a 128bit wide module
+ signal wr_loc, rd_loc : natural range 0 to ((2*1024*1024*1024)/128)-1;
+
begin
+ --Tie the address pins as required by ug388 pg. 51
+ c3_p0_cmd_byte_addr(3 downto 0) <= "0000";
+
+ --Keep the clocks synchronised to the FSM
+ c3_p0_cmd_clk <= clk;
+ c3_p0_wr_clk <= clk;
+ c3_p0_rd_clk <= clk;
+
+ Inst_ddr3mem : ddr3mem
+ generic map (
+ C3_P0_MASK_SIZE => MASK_SIZE,
+ C3_P0_DATA_PORT_SIZE => DATA_PORT_SIZE,
+ C3_MEMCLK_PERIOD => 2500,
+ C3_RST_ACT_LOW => 0,
+ DEBUG_EN => 1,
+ C3_CALIB_SOFT_IP => "TRUE",
+ C3_SIMULATION => "FALSE",
+ C3_MEM_ADDR_ORDER => "ROW_BANK_COLUMN",
+ C3_NUM_DQ_PINS => NUM_DQ_PINS,
+ C3_MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
+ C3_MEM_BANKADDR_WIDTH => MEM_BANKADDR_WIDTH
+ )
+ port map (
+ mcb3_dram_dq => mcb3_dram_dq,
+ mcb3_dram_a => mcb3_dram_a,
+ mcb3_dram_ba => mcb3_dram_ba,
+ mcb3_dram_ras_n => mcb3_dram_ras_n,
+ mcb3_dram_cas_n => mcb3_dram_cas_n,
+ mcb3_dram_we_n => mcb3_dram_we_n,
+ mcb3_dram_odt => mcb3_dram_odt,
+ mcb3_dram_cke => mcb3_dram_cke,
+ mcb3_dram_dm => mcb3_dram_dm,
+ mcb3_rzq => mcb3_rzq,
+ mcb3_zio => mcb3_zio,
+ mcb3_dram_dqs => mcb3_dram_dqs_p,
+ mcb3_dram_dqs_n => mcb3_dram_dqs_n,
+ mcb3_dram_ck => mcb3_dram_ck_p,
+ mcb3_dram_ck_n => mcb3_dram_ck_n,
+ mcb3_dram_udqs => mcb3_dram_udqs_p,
+ mcb3_dram_udqs_n => mcb3_dram_udqs_n,
+ mcb3_dram_udm => mcb3_dram_udm,
+ mcb3_dram_reset_n => mcb3_dram_reset_n,
- Inst_adcwrbuf : memfifo
+ c3_sys_clk => ddrclk,
+ c3_sys_rst_i => sys_rst,
+ c3_calib_done => c3_calib_done,
+ c3_clk0 => c3_clk0,
+ c3_rst0 => c3_rst0,
+
+ c3_p0_cmd_clk => c3_p0_cmd_clk,
+ c3_p0_cmd_en => c3_p0_cmd_en,
+ c3_p0_cmd_instr => c3_p0_cmd_instr,
+ c3_p0_cmd_bl => c3_p0_cmd_bl,
+ c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
+ c3_p0_cmd_empty => c3_p0_cmd_empty,
+ c3_p0_cmd_full => c3_p0_cmd_full,
+
+ c3_p0_wr_clk => c3_p0_wr_clk,
+ c3_p0_wr_en => c3_p0_wr_en,
+ c3_p0_wr_mask => c3_p0_wr_mask,
+ c3_p0_wr_data => c3_p0_wr_data,
+ c3_p0_wr_full => c3_p0_wr_full,
+ c3_p0_wr_empty => c3_p0_wr_empty,
+ c3_p0_wr_count => c3_p0_wr_count,
+ c3_p0_wr_underrun => c3_p0_wr_underrun,
+ c3_p0_wr_error => c3_p0_wr_error,
+
+ c3_p0_rd_clk => c3_p0_rd_clk,
+ c3_p0_rd_en => c3_p0_rd_en,
+ c3_p0_rd_data => c3_p0_rd_data,
+ c3_p0_rd_full => c3_p0_rd_full,
+ c3_p0_rd_empty => c3_p0_rd_empty,
+ c3_p0_rd_count => c3_p0_rd_count,
+ c3_p0_rd_overflow => c3_p0_rd_overflow,
+ c3_p0_rd_error => c3_p0_rd_error
+ );
+
+
+ Inst_adcwrbuf : mem64to128fifo
port map (
- rst => sys_rst,
- wr_clk => adc_wr_clk,
- rd_clk => adc_wrbuf_clk,
- din => adc_wr_data,
- wr_en => adc_wr_en,
- rd_en => adc_wrbuf_en,
- dout => adc_wrbuf_data,
- full => adc_wrbuf_full,
- empty => adc_wrbuf_empty
+ rst => sys_rst,
+
+ wr_clk => adc_wr_clk,
+ wr_en => adc_wr_en,
+ din => adc_wr_data,
+
+ rd_clk => clk,
+ rd_en => adc_wrbuf_en,
+ dout => adc_wrbuf_data,
+
+ full => adc_wrbuf_full,
+ empty => adc_wrbuf_empty,
+ rd_data_count => adc_wrbuf_rd_count,
+ wr_data_count => adc_wrbuf_wr_count
);
- Inst_adcrdbuf : memfifo
+ Inst_adcrdbuf : mem128to64fifo
port map (
- rst => sys_rst,
- wr_clk => adc_rdbuf_clk,
- rd_clk => adc_rd_clk,
- din => adc_rdbuf_data,
- wr_en => adc_rdbuf_en,
- rd_en => adc_rd_en,
- dout => adc_rd_data,
- full => adc_rdbuf_full,
- empty => adc_rdbuf_empty
+ rst => sys_rst,
+
+ wr_clk => clk,
+ wr_en => adc_rdbuf_en,
+ din => adc_rdbuf_data,
+
+ rd_clk => adc_rd_clk,
+ rd_en => adc_rd_en,
+ dout => adc_rd_data,
+
+ full => adc_rdbuf_full,
+ empty => adc_rdbuf_empty,
+ rd_data_count => adc_rdbuf_rd_count,
+ wr_data_count => adc_rdbuf_wr_count
);
ctrl : process(clk, sys_rst)
begin
if clk'event and clk = '1' then
if sys_rst = '1' then
- state <= st0_default;
+ state <= st0_default;
+ adc_wrbuf_en <= '0';
+ adc_rdbuf_en <= '0';
+ c3_p0_cmd_en <= '0';
+ c3_p0_wr_en <= '0';
+ c3_p0_rd_en <= '0';
+ wr_loc <= 0;
+ rd_loc <= 0;
else
case state is
when st0_default =>
- if adc_wrbuf_empty = '0' then
+ adc_wrbuf_en <= '0';
+ adc_rdbuf_en <= '0';
+ c3_p0_cmd_en <= '0';
+ c3_p0_wr_en <= '0';
+ c3_p0_rd_en <= '0';
+
+ if adc_wrbuf_empty = '0' and c3_p0_wr_full = '0' then
state <= st1_write;
- elsif adc_rdbuf_empty = '0'
+ elsif adc_rdbuf_full = '0' and c3_p0_rd_full = '0' then
state <= st1_read;
end if;
+
when st1_read =>
+
when st1_write =>
+ if adc_wrbuf_empty = '1' then
+ state <= st0_default;
+ else
+ if c3_p0_wr_full = '0' then
+ adc_wrbuf_en <= '1';
+ c3_p0_wr_en <= '1';
+ c3_p0_wr_mask <= x"FFFF";
+ c3_p0_wr_data <= adc_wrbuf_data;
+ else
+ adc_wrbuf_en <= '0';
+ c3_p0_wr_en <= '0';
+ if c3_p0_cmd_empty = '0' then
+ c3_p0_cmd_en <= '1';
+ c3_p0_cmd_instr <= CMD_WRITE;
+ c3_p0_cmd_byte_addr(29 downto 4) <= std_logic_vector(to_unsigned(wr_loc, 25));
+ c3_p0_cmd_bl <= "111111";
+ state <= st0_default;
+ end if;
+ end if;
+ end if;
+
end case;
end if;
end if;
View
2  xc6/syn/ipcore_dir/adcdatafifo.xise
@@ -20,7 +20,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="adcdatafifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
View
219 xc6/syn/ipcore_dir/mem128to64fifo.xco
@@ -0,0 +1,219 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.4
+# Date: Tue Apr 17 18:03:28 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:fifo_generator:8.4
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=mem128to64fifo
+CSET data_count=false
+CSET data_count_width=7
+CSET disable_timing_violations=true
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=5
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_handshake_flag_options_axis=false
+CSET enable_handshake_flag_options_rach=false
+CSET enable_handshake_flag_options_rdch=false
+CSET enable_handshake_flag_options_wach=false
+CSET enable_handshake_flag_options_wdch=false
+CSET enable_handshake_flag_options_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=125
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=124
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=128
+CSET input_depth=128
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=64
+CSET output_depth=256
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=Empty
+CSET programmable_empty_type_rach=Empty
+CSET programmable_empty_type_rdch=Empty
+CSET programmable_empty_type_wach=Empty
+CSET programmable_empty_type_wdch=Empty
+CSET programmable_empty_type_wrch=Empty
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=Full
+CSET programmable_full_type_rach=Full
+CSET programmable_full_type_rdch=Full
+CSET programmable_full_type_wach=Full
+CSET programmable_full_type_wdch=Full
+CSET programmable_full_type_wrch=Full
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=9
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=8
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-22T06:08:52Z
+# END Extra information
+GENERATE
+# CRC: b4621401
View
73 xc6/syn/ipcore_dir/mem128to64fifo.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="mem128to64fifo.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="mem128to64fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem128to64fifo|mem128to64fifo_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="mem128to64fifo.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem128to64fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="mem128to64fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-17T18:04:54" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6C45C5B1E819A5D013D9A2553C931DAD" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
View
26 xc6/syn/ipcore_dir/memfifo.xco → xc6/syn/ipcore_dir/mem64to128fifo.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.4
-# Date: Tue Apr 17 17:24:58 2012
+# Date: Tue Apr 17 18:00:39 2012
#
##############################################################
#
@@ -51,9 +51,9 @@ CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
-CSET component_name=memfifo
+CSET component_name=mem64to128fifo
CSET data_count=false
-CSET data_count_width=5
+CSET data_count_width=8
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
@@ -117,14 +117,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=31
+CSET full_threshold_assert_value=255
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=30
+CSET full_threshold_negate_value=254
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
@@ -141,7 +141,7 @@ CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
-CSET input_depth=32
+CSET input_depth=256
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
@@ -150,7 +150,7 @@ CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=128
-CSET output_depth=16
+CSET output_depth=128
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
@@ -173,8 +173,8 @@ CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=4
+CSET read_data_count=true
+CSET read_data_count_width=8
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
@@ -199,7 +199,7 @@ CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
-CSET use_extra_logic=false
+CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
@@ -208,12 +208,12 @@ CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=5
+CSET write_data_count=true
+CSET write_data_count_width=9
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-10-22T06:08:52Z
# END Extra information
GENERATE
-# CRC: 2d41fb11
+# CRC: 9b995d5c
View
73 xc6/syn/ipcore_dir/mem64to128fifo.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="mem64to128fifo.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="mem64to128fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem64to128fifo|mem64to128fifo_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="mem64to128fifo.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem64to128fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="mem64to128fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-17T18:02:05" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5C42B0685037040026ED9553D723DA84" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
View
402 xc6/syn/ipcore_dir/memfifo.xise
@@ -1,402 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="memfifo.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="memfifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
- <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
- <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|memfifo|memfifo_a" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="memfifo.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/memfifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
- <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="memfifo" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="memfifo_map.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="memfifo_timesim.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="memfifo_synthesis.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="memfifo_translate.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="memfifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-17T17:26:24" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8A4120A61613DFA1E81BDAAD9DED0695" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
View
79 xc6/syn/scope.xise
@@ -47,27 +47,27 @@
</file>
<file xil_pn:name="../src/adc/adcbclk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../src/adc/adcbuf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../src/adc/adccal.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../src/adc/adcdata.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../src/adc/adcfclk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../src/adc/adc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../sim/adc/adc_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -77,11 +77,11 @@
</file>
<file xil_pn:name="../src/clockbuf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../src/main.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../sim/clockbuf_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -100,7 +100,7 @@
</file>
<file xil_pn:name="../src/ddr3mem/ddr3mem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../src/ddr3mem/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -124,11 +124,11 @@
</file>
<file xil_pn:name="../src/ddr3mem/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../src/ddr3mem/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../sim/ddr3mem/afifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -240,11 +240,11 @@
</file>
<file xil_pn:name="../src/think.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../src/fx3.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../sim/think_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -254,45 +254,49 @@
</file>
<file xil_pn:name="ipcore_dir/adcdatafifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../src/datawrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../src/adc/adcspi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../src/input.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../src/monitoring.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="ipcore_dir/cfgfifo16.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../sim/fx3_tb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="ipcore_dir/adcpktfifo.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="ipcore_dir/memfifo.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../src/memwrapper.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+ <file xil_pn:name="ipcore_dir/mem128to64fifo.xco" xil_pn:type="FILE_COREGEN">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="ipcore_dir/mem64to128fifo.xco" xil_pn:type="FILE_COREGEN">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="ipcore_dir/adcdatafifo.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -303,8 +307,11 @@
<file xil_pn:name="ipcore_dir/adcpktfifo.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
- <file xil_pn:name="ipcore_dir/memfifo.xise" xil_pn:type="FILE_COREGENISE">
- <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+ <file xil_pn:name="ipcore_dir/mem128to64fifo.xise" xil_pn:type="FILE_COREGENISE">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="ipcore_dir/mem64to128fifo.xise" xil_pn:type="FILE_COREGENISE">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
@@ -553,8 +560,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/fx3_tb" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.fx3_tb" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/memwrapper" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.memwrapper" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -572,7 +579,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.fx3_tb" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.memwrapper" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -624,7 +631,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|fx3_tb|Behavioral" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|memwrapper|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="scope" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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