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alperyazar committed May 3, 2019
1 parent 57c1050 commit 42df9f5913ad3d5f7e44edcaf97d8837d2901400
Showing with 40 additions and 10 deletions.
  1. +8 −0 docs/bibliography.rst
  2. +32 −10 docs/lectures/dodd-s18-mutlu/lec04.rst
@@ -19,6 +19,7 @@ Journal

.. [hamming1950error] Hamming, R. W. (1950). Error detecting and error correcting codes. The Bell system technical journal, 29(2), 147-160. `Link <>`__
.. [lamport1982byzantine] Lamport, L., Shostak, R., & Pease, M. (1982). The Byzantine generals problem. ACM Transactions on Programming Languages and Systems (TOPLAS), 4(3), 382-401. `Link <>`__
.. [bloom1970space] Bloom, B. H. (1970). Space/time trade-offs in hash coding with allowable errors. Communications of the ACM, 13(7), 422-426. `Link <>`__
@@ -33,6 +34,12 @@ Conference
.. [mutlu2007stall] Mutlu, O., & Moscibroda, T. (2007, December). Stall-time fair memory access scheduling for chip multiprocessors. In Proceedings of the 40th Annual IEEE/ACM international Symposium on Microarchitecture (pp. 146-160). IEEE Computer Society. `Link <>`__
.. [mutlu2008parallelism] Mutlu, O., & Moscibroda, T. (2008, June). Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ACM SIGARCH Computer Architecture News (Vol. 36, No. 3, pp. 63-74). IEEE Computer Society. `Link <>`__
.. [muralidhara2011reducing] Muralidhara, S. P., Subramanian, L., Mutlu, O., Kandemir, M., & Moscibroda, T. (2011, December). Reducing memory interference in multicore systems via application-aware memory channel partitioning. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 374-385). ACM. `Link <>`__
.. [chang2014improving] Chang, K. K. W., Lee, D., Chishti, Z., Alameldeen, A. R., Wilkerson, C., Kim, Y., & Mutlu, O. (2014, February). Improving DRAM performance by parallelizing refreshes with accesses. In 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) (pp. 356-367). IEEE. `Link <>`__

.. [zuravleff1997controller] Zuravleff, W. K., & Robinson, T. (1997). U.S. Patent No. 5,630,096. Washington, DC: U.S. Patent and Trademark Office. `Link <>`__
@@ -43,3 +50,4 @@ Other
.. [horn2018reading] Horn, J. (2018). Reading privileged memory with a side-channel. Project Zero, 3. `Link <>`__
.. [seaborn2015exploiting] Seaborn, M., & Dullien, T. (2015). Exploiting the DRAM rowhammer bug to gain kernel privileges. Black Hat, 15. `Link <>`__
.. [liu2012raidr] Liu, J., Jaiyen, B., Veras, R., & Mutlu, O. (2012, June). RAIDR: Retention-aware intelligent DRAM refresh. In ACM SIGARCH Computer Architecture News (Vol. 40, No. 3, pp. 1-12). IEEE Computer Society. `Link <>`__
.. [mutlu2013memory] Mutlu, O. (2013, May). Memory scaling: A systems architecture perspective. In 2013 5th IEEE International Memory Workshop (pp. 21-25). IEEE. `Link <>`__
@@ -3,10 +3,6 @@
Lecture 04 - Mysteries in Comp Arch and Basics

.. warning::
Incomplete. Stopped at 1:01:00


@@ -24,7 +20,11 @@ Reading
* [mutlu2008parallelism]_
* [muralidhara2011reducing]_
* [liu2012raidr]_

* [mutlu2013memory]_
* [chang2014improving]_
* [bloom1970space]_
* [zuravleff1997controller]_ (Couldn't notice during lecture, I added as
reference since it is stated on course page)

Reading Notes
@@ -150,28 +150,50 @@ Lecture Minutes
* **51:15** Do we have to refresh every row every 64 ms? What if all memory
isn't allocated? Today, this information from OS (page table) doesn't get
into the memory controller.

* **53:00** It looks like very small portion of rows should be refreshed
at 64 ms. Refresh time of most rows is greater than 256 ms. Why? Because of
imperfections during manufacturing. This is *Manufacturing Process Variation*
As process' nanometer decreases, imperfections increases. This is also true
for processor speed variation between processors.

* **55:30** **Cold boot attack** is mentioned as side note.

* **56:30** Assume we know the retention time of each row exactly? How can we
use this information? At which layer?

* **1:00:45** We are refreshing all rows at every 64 ms although very small
portion needs that much frequent refresh. Most of them can be refreshed at
256 ms. One proposal is **RAIDR**: Refresh ony weak rows more frequently.
* **1:01:00** Read: [liu2012raidr]_
* **1:01:00** Read: [liu2012raidr]_ For RAIDR approach 1) you profile DRAM and
identify rows. 2) you should store row profile information in an efficient
and scalable way (Hint: Bloom Filters). For this case 1.25 KB storage is
sufficient for 32GB DRAM memory. 3) refresh accordingly.
* **1:30:10** 74.6/ refresh reduction and some power reduction is achieved.
* **1:05:20** Really interested? [mutlu2013memory]_, [chang2014improving]_
* **1:05:40** Cooperation between multiple layers leads to more effective
* **1:08:08** Talk about :term:`bloom filters` started. *Approximate Set
Membership*. You can tolerate false positive (although a member is not in the
send, you find that it belongs to the set). You can not tolerate false
negative (element in the set but you think that it isn't). You want to
control false positive rate but don't want any false negative.
* **1:16:00** Start of Bloom Filter example on board with chalk. Nice example,
worth watching.
* **1:28:20** Original idea: [bloom1970space]_ It is a probabilistic data
structure that compactly represents set membership. Notice that solution to
RowHammer problem also includes a probabilistic solution.


.. glossary::

bloom filters

Developed late 1960s. It is mentioned last ~20 minutes of the lecture.
See the notes.

.. todo::

I may write a separate page about Bloom filters.

streaming application
Application that reaches memory regions with high locality. For example
accessing x[i] while i is increasing like i++ is a streaming

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