diff --git a/catalog/list.json b/catalog/list.json
index 7c666f9..b2a4e43 100644
--- a/catalog/list.json
+++ b/catalog/list.json
@@ -1,5 +1,5 @@
 {
-    "num": 186,
+    "num": 204,
     "designs": [
         {
             "id": "763954",
@@ -4318,6 +4318,348 @@
             "Q_DOWNLOAD_URL": "https://cdrdv2.intel.com/v1/dl/getContent/850281?explicitVersion=true&fileName=top.par",
             "Q_VALIDATED": true
         },
+        {
+            "id": "-",
+            "title": "Nios® V/c Processor PIO & OCM Test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1 Pro",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core along with OCM Memory test.",
+            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. Additionally, the OCM memory tests are performed.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_c/pio_ocm/pio.png\"/></p>",
+            "category": "PIO LED Toggle",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/25.1.1-v1.0/agf014ea-dev-devkit/niosv_c/pio_ocm/docs/Nios_Vc_Processor_PIO_OCM_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_c_pio_ocm.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291413003",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Custom Instruction CRC Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based custom instruction Cyclic Redundancy Check (CRC) example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>A Processing Engine (PE) that performs the Cyclic Redundancy Check (CRC) algorithm is connected to the Nios® V/g processor using the custom instruction interface</p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_crc/img/ci_crc/img/agilex7_ci_crc.png\"/></p>",
+            "category": "Web Server",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/25.1.1-v1.0/agf014ea-dev-devkit/niosv_g/ci_crc/docs/Nios_Vg_Processor_CI_CRC_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_g_ci_crc.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291405074",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Custom Instruction Basic Operations Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based custom instruction example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>A Processing Engine (PE) that performs basic arithmetic and logical computations is connected to the Nios® V/g processor using the custom instruction interface. </p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/img/agilex7_ci_basic_operations.png\"/></p>",
+            "category": "Custom Instruction",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/25.1.1-v1.0/agf014ea-dev-devkit/niosv_g/ci_basic_operations/docs/Nios_Vg_Processor_CI_Basic_Operations_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_ci_basic_operations.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291397552",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/g Processor ECC Lite test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Agilex 7 FPGA - ECC Lite Design Example on Nios® V/g Processor",
+            "rich_description": "<p>This design demonstrates the ECC Lite feature of the Nios® V/g core by injecting an error on the General-Purpose Register (GPR) via simulation.</p><p>The ECC status and ECC source is observed for both correctable and uncorrectable errors on the General-Purpose Registers (GPR).</p><p>The Error is injected on the OCM (M20k) GPR through the ECC parity flip feature. The parity value in the GPR is flipped using the force command in the test bench file (sys_tb.v). </p><p>The ECC Status and ECC Source signals are probed and observed using Questa Simulation</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/agilex7_ecc_lite/img/agilex7_ecc_lite.png\"/></p>",
+            "category": "ECC",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ecc_lite_test/docs/NiosV_g_Processor_ECC_Lite_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_ecc_lite.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290940866",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/g Processor Floating Point Unit (FPU) Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/g Processor-based design example with Floating Point Unit (FPU) on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
+            "rich_description": "<p>This example design is about applying the floating point unit in Nios V/g processor. The example application evaluates the floating point rate of Nios V/g processor by using Linpack benchmark.\n More information on the Linpack Benchmark can be found here- https://top500.org/project/linpack/</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_g/fpu_test/img/block_diagram.png\"/></p>",
+            "category": "FPU",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014eb-si-devkit/niosv_g/fpu_test/docs/NiosV_g_Processor_Floating_Point_Unit_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_g_fpu_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290947492",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Tightly Coupled Memory (TCM) Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based TCM example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>This example design is about how to use tightly coupled memory in Nios® V/g processor. The example application measures the memory access speed of different memories connected to the processor, such as TCM, on-chip memory and external memory interface (EMIF). In addition to that, the application showcases the speedup between cached and un-cached memories.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_g/tcm_mem_test/img/agilex7_tcm.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014eb-si-devkit/niosv_g/tcm_mem_test/docs/NiosV_g_Processor_Tightly_Coupled_Memory_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_tcm.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291236753",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
+            "category": "Machine Learning",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/25.1.1-v1.0/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291414938",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Hello World Example Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/g Processor-based Hello World example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>Nios® V/g Processor-based Helloworld example design on the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/hello_world/img/hello_world.png\"/></p>",
+            "category": "Hello World",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_g/hello_world/docs/Nios_Vg_Processor_Hello_World_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_g_hello_world.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290930424",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 7 FPGA - Hello World Example Design Example on Nios® V/m Processor",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios® V/m Processor-based Hello World example design on the Agilex® 7 FPGA.",
+            "rich_description": "<p>Nios® V/m Processor-based Helloworld example design on the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/hello_world/img/hello_world.png\"/></p>",
+            "category": "Hello World",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/hello_world/docs/Nios_Vm_Processor_Hello_World_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_hello_world.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290925870",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor DMA - OCM Memory test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/m Processor-based Direct Memory Access (DMA) and On-Chip Memory (OCM) Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the 2 On Chip RAM using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/dma_ocm_mem_test/img/block_diagram.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/dma_ocm_mem_test/docs/NiosV_m_Processor_OCM_Memory_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_dma_ocm_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290951914",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor OCM to OCM Memory test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/m Processor-based On-Chip Memory (OCM) Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the OCM and JTAG UART IP. \nThe objective of the design is to write and read into specific locations of On Chip RAM. This implementation of On Chip RAM uses the Avalon interface.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ocm_mem_test/img/block_diagram.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ocm_mem_test/docs/NiosV_m_Processor_OCM_Memory_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_ocm_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290944187",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor PIO LED toggle Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core.",
+            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/pio_test/img/pio.png\"/></p>",
+            "category": "PIO LED Toggle",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/pio_test/docs/NiosV_m_Processor_PIO_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_pio_led_toggle.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290937863",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor Timer Interval Interrupt Test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/m Processor-based Timer Interrupt design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the Interval Timer IP to issue alarm-based interrupt to the NIOSV/m core. \nThe objective of the design is to demonstrate the interrupt behavior and handling by the Nios V embedded processor. Once the interrupt is issued; the Nios V prints the system ID of the SYS ID peripheral core.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/isr_test/img/block_diagram.png\"/></p>",
+            "category": "Timer",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/isr_test/docs/NiosV_m_Processor_Timer_Interval_Interrupt_Test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_isr_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290854574",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Iperf Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client.",
+            "rich_description": "<p>An iPerf server receives an iPerf request sent over a TCP/IP connection from any iPerf clients and runs the iPerf test according to the provided arguments.\n Each test reports the bandwidth, loss, and other parameters. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf/img/agilex7_iperf.png\"/></p>",
+            "category": "Web Server",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf/docs/NiosV_m_Processor_Iperf_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_sisoc_iperf.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290881313",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m SSS Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Simple Socket Server design on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
+            "rich_description": "<p>The telnet client offers a convenient way of issuing commands over a TCP/IP socket to the Ethernet-connected μC/TCP-IP running on the development board with a simple TCP/IP socket server example. \n The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. \n The example consists of a socket server task that listens for commands on a TCP/IP port and dispatches those commands to a set of LED management tasks.  </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/img/agilex7_sss.png\"/></p>",
+            "category": "Web Server",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/docs/NiosV_m_Processor_SSS_Design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_sisoc_sss.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290922946",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor Transceiver Loopback design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
+            "device_part": "AGFB027R24C2E2VR2",
+            "description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
+            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
+            "category": "Transceiver",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs",
+            "downloadUrl": "agilex7_xcver_loopback.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290924003",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor EMIF data mover Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/m Processor-based External Memory Interface (EMIF) data mover example design on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the External Memory Interface (EMIF), DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the On Chip RAM and the DDR (EMIF) using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p>This design uses the Nios V processor hosted on the fabric to communicate with the external memory-DDR micron module. \nThe code is booted from the on-chip memory, whereas the Nios V processor carries out certain transactions to and from the DDR using the EMIF controller.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/emif_mem_test/img/block_diagram.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/emif_mem_test/docs/NiosV_m_Processor_OCM_Memory_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_emif_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291294615",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Processor DDR,DMA and OCM Memory test Design",
+            "source": "GitHub",
+            "family": "Agilex 7",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "device_part": "AGFB014R24B2E2V",
+            "description": "Nios V/m Processor-based Memory Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
+            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the External Memory Interface (EMIF), DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the On Chip RAM and the DDR (EMIF) using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ddr_dma_ocm_mem_test/img/block_diagram.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ddr_dma_ocm_mem_test/docs/NiosV_m_Processor_OCM_Memory_test_Example_design_on_Agilex_7_FPGA.md",
+            "downloadUrl": "agilex7_niosv_m_ddr_dma_ocm_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291294306",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
         {
             "id": "-",
             "title": "Nios® V/g Processor Floating Point Unit (FPU) Design",