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FogBugz #294156: Enable watchdog on Arria10

Enable watchdog timer on Arria10. On the A10, only watchdog1 is able to
trigger a reset reliably.

Also, there is a dependency on the bootloader to enable the boot_clk
source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN | SWCTRLBTCLKSEL) bits enabled
in the clock manager.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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1 parent 61562cb commit 1a885c87c7b837c9f191f105bfa794c2e81fbe2e Dinh Nguyen committed May 29, 2015
Showing with 6 additions and 0 deletions.
  1. +2 −0 arch/arm/boot/dts/socfpga_arria10.dtsi
  2. +4 −0 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -711,13 +711,15 @@
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
};
@@ -242,3 +242,7 @@
&uart1 {
status = "okay";
};
+
+&watchdog1 {
+ status = "okay";
+};

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