FogBugz #288412: Add correct reset manager offsets for Arria10

There are 2 peripheral module reset manager registers on the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: use socfpga_is_a10() and cleanup Conflicts: arch/arm/mach-socfpga/core.h arch/arm/mach-socfpga/socfpga.c
altera-opensource · Apr 7, 2015 · da93558 · da93558
1 parent 0e9c1d9
commit da93558
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Showing 2 changed files with 17 additions and 2 deletions.
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,9 @@
 #define SOCFPGA_RSTMGR_BRGMODRST	0x1c
 
 #define SOCFPGA_A10_RSTMGR_CTRL		0xC
+#define SOCFPGA_A10_RSTMGR_PER0MODRST	0x24
+#define SOCFPGA_A10_RSTMGR_PER1MODRST	0x28
+#define SOCFPGA_A10_RSTMGR_BRGMODRST	0x2C
 
 /* System Manager bits */
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
@@ -40,6 +40,8 @@ void __iomem *sdr_ctl_base_addr;
 void __iomem *l3regs_base_addr;
 void __iomem *clkmgr_base_addr;
 
+static int socfpga_is_a10(void);
+
 #ifdef CONFIG_HW_PERF_EVENTS
 static struct arm_pmu_platdata socfpga_pmu_platdata = {
 	.handle_irq = socfpga_pmu_handler,
@@ -127,8 +129,18 @@ static void __init socfpga_scu_map_io(void)
 
 static void __init enable_periphs(void)
 {
-	/* Release all peripherals from reset.*/
+	if (socfpga_is_a10()) {
-	__raw_writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+		/* temp hack to enable all periphs from reset for A10 */
+		writel(0x0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_PER0MODRST);
+		writel(0x0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_PER1MODRST);
+	} else {
+		writel(0x0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+	}
+}
+
+static int socfpga_is_a10(void)
+{
+	return of_machine_is_compatible("altr,socfpga-arria10");
 }
 
 static void __init socfpga_map_io(void)