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FogBugz #288412: Add correct reset manager offsets for Arria10

There are 2 peripheral module reset manager registers on the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: use socfpga_is_a10() and cleanup
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1 parent 512a3b0 commit eebb91461a3fdcf87d627c9dab92e0b90f519116 Dinh Nguyen committed Mar 25, 2015
Showing with 11 additions and 3 deletions.
  1. +2 −0 arch/arm/mach-socfpga/core.h
  2. +9 −3 arch/arm/mach-socfpga/socfpga.c
@@ -26,6 +26,8 @@
#define SOCFPGA_A10_RSTMGR_CTRL 0xC
#define SOCFPGA_A10_RSTMGR_PER0MODRST 0x24
+#define SOCFPGA_A10_RSTMGR_PER1MODRST 0x28
+#define SOCFPGA_A10_RSTMGR_BRGMODRST 0x2C
/* System Manager bits */
#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
@@ -52,6 +52,10 @@ unsigned long cpu1start_addr;
static int stmmac_plat_init(struct platform_device *pdev);
static void stmmac_fix_mac_speed(void *priv, unsigned int speed);
+static int socfpga_is_a5(void);
+static int socfpga_is_c5(void);
+static int socfpga_is_a10(void);
+
static struct plat_stmmacenet_data stmmacenet0_data = {
.init = &stmmac_plat_init,
.bus_id = 0,
@@ -172,11 +176,13 @@ static void __init enable_periphs(void)
u32 rstval;
rstval = RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1;
- if (of_machine_is_compatible("altr,socfpga-arria10"))
+ if (socfpga_is_a10()) {
/* temp hack to enable all periphs from reset for A10 */
- writel(0x0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
- else
+ writel(0x0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_PER0MODRST);
+ writel(0x0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_PER1MODRST);
+ } else {
writel(rstval, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+ }
}
#define MICREL_KSZ9021_EXTREG_CTRL 11

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