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FogBugz #336111: Remove used defconfig and dts

Removed defconfig and dts for Arria 10 dedicated
UART configuration. Dedicated UART will be used
within default configuration as its supported by
Altera Arria10 SoC rev B1 dev kit.

Signed-off-by: Chin Liang See <clsee@altera.com>
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1 parent 1528200 commit 2724a740b8dd8bd69a98d0ad06d1a8b258d859ec Chin Liang See committed Nov 19, 2015
@@ -1,271 +0,0 @@
-/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-
-/ {
- model = "SOCFPGA Arria10 Dev Kit";
-
-
- chosen {
- cff-file = "ghrd_10as066n2.periph.rbf",
- "ghrd_10as066n2.core.rbf";
- /* external-fpga-config; */
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
-
- altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>; /* 25.00 MHz */
- clock-output-names = "arria10_hps_0_eosc1-clk";
- };
- };
-
-
- pinmux@0xffd07000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "pinctrl-single";
- shared {
- reg = <0xffd07000 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- <0x00000000 0x00000008>,
- <0x00000004 0x00000008>,
- <0x00000008 0x00000008>,
- <0x0000000c 0x00000008>,
- <0x00000010 0x00000008>,
- <0x00000014 0x00000008>,
- <0x00000018 0x00000008>,
- <0x0000001c 0x00000008>,
- <0x00000020 0x00000008>,
- <0x00000024 0x00000008>,
- <0x00000028 0x00000008>,
- <0x0000002c 0x00000008>,
- <0x00000030 0x00000004>,
- <0x00000034 0x00000004>,
- <0x00000038 0x00000004>,
- <0x0000003c 0x00000004>,
- <0x00000040 0x00000004>,
- <0x00000044 0x00000004>,
- <0x00000048 0x00000004>,
- <0x0000004c 0x00000004>,
- <0x00000050 0x00000004>,
- <0x00000054 0x00000004>,
- <0x00000058 0x00000004>,
- <0x0000005c 0x00000004>,
- <0x00000060 0x00000003>,
- <0x00000064 0x00000003>,
- <0x00000068 0x00000003>,
- <0x0000006c 0x00000003>,
- <0x00000070 0x00000003>,
- <0x00000074 0x0000000f>,
- <0x00000078 0x0000000a>,
- <0x0000007c 0x0000000a>,
- <0x00000080 0x0000000f>,
- <0x00000084 0x0000000f>,
- <0x00000088 0x00000001>,
- <0x0000008c 0x00000001>,
- <0x00000090 0x00000000>,
- <0x00000094 0x00000000>,
- <0x00000098 0x0000000f>,
- <0x0000009c 0x0000000c>,
- <0x000000a0 0x0000000f>,
- <0x000000a4 0x0000000f>,
- <0x000000a8 0x0000000f>,
- <0x000000ac 0x0000000f>,
- <0x000000b0 0x0000000c>,
- <0x000000b4 0x0000000c>,
- <0x000000b8 0x0000000c>,
- <0x000000bc 0x0000000c>;
-
- };
-
- dedicated {
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- <0x0000000c 0x00000008>,
- <0x00000010 0x00000008>,
- <0x00000014 0x00000008>,
- <0x00000018 0x00000008>,
- <0x0000001c 0x00000008>,
- <0x00000020 0x00000008>,
- <0x00000024 0x00000008>,
- <0x00000028 0x0000000f>,
- <0x0000002c 0x0000000f>,
- <0x00000030 0x0000000f>,
- <0x00000034 0x0000000f>,
- <0x00000038 0x0000000f>,
- <0x0000003c 0x0000000d>,
- <0x00000040 0x0000000d>;
-
- };
-
- dedicated_cfg {
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x003f3f3f>;
- pinctrl-single,pins =
- <0x00000100 0x00000101>,
- <0x00000104 0x000d0000>,
- <0x00000108 0x000d0000>,
- <0x00000110 0x000a0304>,
- <0x00000114 0x000a0304>,
- <0x00000118 0x000a0304>,
- <0x0000011c 0x000a0304>,
- <0x00000120 0x000a0304>,
- <0x00000124 0x000a0304>,
- <0x00000128 0x00090304>,
- <0x0000012c 0x000d0008>,
- <0x00000130 0x000d0008>,
- <0x00000134 0x000d0008>,
- <0x00000138 0x000d0008>,
- <0x0000013c 0x000d0008>,
- <0x00000140 0x00082808>,
- <0x00000144 0x000a0000>;
-
- };
-
- fpga {
- reg = <0xffd07400 0x00000100>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000001>;
- pinctrl-single,pins =
- <0x00000000 0x00000000>,
- <0x00000004 0x00000000>,
- <0x00000008 0x00000000>,
- <0x0000000c 0x00000000>,
- <0x00000010 0x00000000>,
- <0x00000014 0x00000000>,
- <0x00000018 0x00000000>,
- <0x0000001c 0x00000000>,
- <0x00000020 0x00000000>,
- <0x00000024 0x00000000>,
- <0x00000028 0x00000000>,
- <0x0000002c 0x00000000>,
- <0x00000030 0x00000000>,
- <0x00000034 0x00000000>,
- <0x00000038 0x00000000>,
- <0x0000003c 0x00000000>,
- <0x00000040 0x00000000>;
-
- };
-
- };
-
- clock_manager@ffd04000 {
- compatible = "altr,socfpga-a10-clk-init";
-
- mainpll {
- vco0-psrc = <0>;
- vco1-denom = <1>;
- vco1-numer = <191>;
- mpuclk-cnt = <0>;
- mpuclk-src = <0>;
- nocclk-cnt = <0>;
- nocclk-src = <0>;
- cntr2clk-cnt = <47>;
- cntr3clk-cnt = <47>;
- cntr4clk-cnt = <23>;
- cntr5clk-cnt = <23>;
- cntr6clk-cnt = <11>;
- cntr7clk-cnt = <23>;
- cntr7clk-src = <0>;
- cntr8clk-cnt = <23>;
- cntr9clk-cnt = <2>;
- cntr9clk-src = <0>;
- cntr15clk-cnt = <23>;
- nocdiv-l4mainclk = <0>;
- nocdiv-l4mpclk = <1>;
- nocdiv-l4spclk = <2>;
- nocdiv-csatclk = <0>;
- nocdiv-cstraceclk = <0>;
- nocdiv-cspdbgclk = <1>;
- };
-
- perpll {
- vco0-psrc = <0>;
- vco1-denom = <1>;
- vco1-numer = <159>;
- cntr2clk-cnt = <7>;
- cntr2clk-src = <1>;
- cntr3clk-cnt = <39>;
- cntr3clk-src = <1>;
- cntr4clk-cnt = <19>;
- cntr4clk-src = <1>;
- cntr5clk-cnt = <499>;
- cntr5clk-src = <1>;
- cntr6clk-cnt = <19>;
- cntr6clk-src = <0>;
- cntr7clk-cnt = <19>;
- cntr8clk-cnt = <19>;
- cntr8clk-src = <0>;
- cntr9clk-cnt = <19>;
- emacctl-emac0sel = <0>;
- emacctl-emac1sel = <0>;
- emacctl-emac2sel = <0>;
- gpiodiv-gpiodbclk = <32000>;
- };
- alteragrp {
- nocclk = <0x50005>;
- mpuclk = <0x10001>;
- };
- };
-
- i_noc: noc@0xffd10000 {
- compatible = "altr,socfpga-a10-noc";
- firewall {
- /* existance of property implies it is enabled */
- /* values are <start end> */
- mpu0 = <0 0xffff>;
- /* mpu1 disabled */
- /* mpu2 disabled */
- /* mpu3 disabled */
- l3-0 = <0 0xffff>;
- /* l3-1 disabled */
- /* l3-2 disabled */
- /* l3-3 disabled */
- /* l3-4 disabled */
- /* l3-5 disabled */
- /* l3-6 disabled */
- /* l3-7 disabled */
- fpga2sdram0-0 = <0 0xffff>;
- /* fpga2sdram0-1 disabled */
- /* fpga2sdram0-2 disabled */
- /* fpga2sdram0-3 disabled */
- fpga2sdram1-0 = <0 0xffff>;
- /* fpga2sdram1-1 disabled */
- /* fpga2sdram1-2 disabled */
- /* fpga2sdram1-3 disabled */
- fpga2sdram2-0 = <0 0xffff>;
- /* fpga2sdram2-1 disabled */
- /* fpga2sdram2-2 disabled */
- /* fpga2sdram2-3 disabled */
- };
- };
-
- hps_fpgabridge0: fpgabridge@0 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- init-val = <1>;
- };
-
- hps_fpgabridge1: fpgabridge@1 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- init-val = <1>;
- };
-
- hps_fpgabridge2: fpgabridge@2 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- init-val = <0>;
- };
-};
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