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  1. +4 −0 Papilio_SOC_Schematic/README.md
  2. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/LogicStart_MegaWing.sym
  3. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/Papilio_Default.sym
  4. +909 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/Papilio_SOC_Base.sch
  5. +565 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/Papilio_SOC_Base.xise
  6. +271 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/ZPUino.sym
  7. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/i2c_master_top.sym
  8. +79 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/papilio_one.ucf
  9. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/vga_zxspectrum.sym
  10. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/wb_sid6581.sym
  11. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_empty_device.sym
  12. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_gpio.sym
  13. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_io_POKEY.sym
  14. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_io_YM2149.sym
  15. +284 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_papilio_pro.sym
  16. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_sevenseg.sym
  17. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_sigmadelta.sym
  18. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_spi.sym
  19. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/zpuino_uart.sym
  20. +1,143 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/LogicStart.sch
  21. +566 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/LogicStart.xise
  22. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/LogicStart_MegaWing.sym
  23. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/Papilio_Default.sym
  24. +271 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/ZPUino.sym
  25. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/i2c_master_top.sym
  26. +79 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/papilio_one.ucf
  27. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/vga_zxspectrum.sym
  28. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/wb_sid6581.sym
  29. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_empty_device.sym
  30. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_gpio.sym
  31. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_io_POKEY.sym
  32. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_io_YM2149.sym
  33. +284 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_papilio_pro.sym
  34. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_sevenseg.sym
  35. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_sigmadelta.sym
  36. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_spi.sym
  37. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_LogicStart/zpuino_uart.sym
  38. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/LogicStart_MegaWing.sym
  39. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/Papilio_Default.sym
  40. +903 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/Papilio_SOC_Base.sch
  41. +176 −149 ...500k_vanilla_ise.xise → Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/Papilio_SOC_Base.xise
  42. +271 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/ZPUino.sym
  43. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/i2c_master_top.sym
  44. +79 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/papilio_one.ucf
  45. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/vga_zxspectrum.sym
  46. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/wb_sid6581.sym
  47. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_empty_device.sym
  48. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_gpio.sym
  49. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_io_POKEY.sym
  50. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_io_YM2149.sym
  51. +284 −0 Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_papilio_pro.sym
  52. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_sevenseg.sym
  53. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_sigmadelta.sym
  54. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_spi.sym
  55. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_one_500k_base/zpuino_uart.sym
  56. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/LogicStart_MegaWing.sym
  57. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/Papilio_Default.sym
  58. +1,008 −0 Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/Papilio_SOC_Base.sch
  59. +650 −0 Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/Papilio_SOC_Base.xise
  60. +271 −0 Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/ZPUino.sym
  61. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/i2c_master_top.sym
  62. +130 −0 Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/papilio_pro.ucf
  63. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/vga_zxspectrum.sym
  64. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/wb_sid6581.sym
  65. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_empty_device.sym
  66. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_gpio.sym
  67. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_io_POKEY.sym
  68. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_io_YM2149.sym
  69. +284 −0 Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_papilio_pro.sym
  70. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_sevenseg.sym
  71. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_sigmadelta.sym
  72. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_spi.sym
  73. BIN  Papilio_SOC_Schematic/example_SOCs/papilio_pro_lx9_base/zpuino_uart.sym
  74. +190 −0 Papilio_SOC_Schematic/hardware/LogicStart_MegaWing.vhd
  75. +179 −0 Papilio_SOC_Schematic/hardware/Papilio_Default.vhd
  76. BIN  Papilio_SOC_Schematic/xilinx_libs/LogicStart_MegaWing.sym
  77. BIN  Papilio_SOC_Schematic/xilinx_libs/Papilio_Default.sym
  78. +25 −0 Papilio_SOC_Schematic/xilinx_libs/Papilio_SOC.cat
  79. +1,194 −0 Papilio_SOC_Schematic/xilinx_libs/Papilio_SOC.lib
  80. +271 −0 Papilio_SOC_Schematic/xilinx_libs/ZPUino.sym
  81. BIN  Papilio_SOC_Schematic/xilinx_libs/i2c_master_top.sym
  82. BIN  Papilio_SOC_Schematic/xilinx_libs/vga_zxspectrum.sym
  83. BIN  Papilio_SOC_Schematic/xilinx_libs/wb_sid6581.sym
  84. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_empty_device.sym
  85. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_gpio.sym
  86. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_io_POKEY.sym
  87. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_io_YM2149.sym
  88. +284 −0 Papilio_SOC_Schematic/xilinx_libs/zpuino_papilio_pro.sym
  89. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_sevenseg.sym
  90. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_sigmadelta.sym
  91. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_spi.sym
  92. BIN  Papilio_SOC_Schematic/xilinx_libs/zpuino_uart.sym
  93. 0  {Papilio → Papilio_SOC_VHDL}/papilio_one_250k_vanilla_ise/papilio_one_250k_vanilla_ise.xise
  94. +386 −0 Papilio_SOC_VHDL/papilio_one_500k_vanilla_ise/papilio_one_500k_vanilla_ise.xise
  95. 0  {Papilio → Papilio_SOC_VHDL}/papilio_pro_lx9_vanilla_ise/papilio_pro_lx9_vanilla_ise.xise
  96. +5 −9 Readme.txt
  97. +0 −5 misc/ChangeLog
  98. +0 −31 misc/arm7/src/arm7pkg.vhd
  99. +0 −236 misc/arm7/src/arm7wb.vhd
  100. +0 −16 misc/ddrsdram/simscripts/ddr_tb.do
  101. +0 −104 misc/ddrsdram/simscripts/ddr_top.do
  102. +0 −301 misc/ddrsdram/simsrc/ddr_tb.vhd
  103. +0 −107 misc/ddrsdram/src/ddr_pkg.vhd
  104. +0 −743 misc/ddrsdram/src/ddr_top.vhd
  105. +0 −1,320 misc/ddrsdram/src/mt46v16m16.vhd
  106. +0 −20 misc/readme.txt
  107. +0 −132 misc/wishbone/src/atomic32_access.vhd
  108. +0 −52 misc/wishbone/src/wishbone_pkg.vhd
  109. +0 −11 wip/.project
  110. +44 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/Makefile
  111. +56 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/bootloader.vhd
  112. +215 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/clkgen.vhd
  113. +72 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/papilio_pro.prj
  114. +130 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/papilio_pro.ucf
  115. +22 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/papilio_pro.ut
  116. +51 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/papilio_pro.xst
  117. +160 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/prom-generic-dp-32.vhd
  118. +738 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/sdram_hamster.vhd
  119. +151 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/sdram_wrap.vhd
  120. +65 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/stack.vhd
  121. +254 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/tb.vhd
  122. +96 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/wb_bootloader.vhd
  123. +68 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/zpu_config.vhd
  124. +76 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/zpuino_config.vhd
  125. +1,192 −0 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/papilio_soc/zpuino_papilio_pro.vhd
  126. +372 −98 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/vanilla/papilio_pro.ucf
  127. +79 −21 zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/vanilla/papilio_pro_top.vhd
  128. +41 −0 zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/Makefile
  129. +88 −0 zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/Papilio_SOC.sch
  130. +217 −0 zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/clkgen.vhd
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4 Papilio_SOC_Schematic/README.md
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+Papilio_System_On_Chip
+======================
+
+Build your custom Arduino compatible microcontroller using a schematic editor.
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909 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/Papilio_SOC_Base.sch
@@ -0,0 +1,909 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan3e" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="XLXN_13(31:0)" />
+ <signal name="XLXN_14(31:0)" />
+ <signal name="XLXN_15(26:2)" />
+ <signal name="XLXN_16" />
+ <signal name="XLXN_17" />
+ <signal name="XLXN_18" />
+ <signal name="XLXN_19" />
+ <signal name="XLXN_20" />
+ <signal name="XLXN_39" />
+ <signal name="XLXN_40" />
+ <signal name="XLXN_41(31:0)" />
+ <signal name="XLXN_42(31:0)" />
+ <signal name="XLXN_43(26:2)" />
+ <signal name="XLXN_44" />
+ <signal name="XLXN_45" />
+ <signal name="XLXN_46" />
+ <signal name="XLXN_47" />
+ <signal name="XLXN_48" />
+ <signal name="XLXN_49" />
+ <signal name="XLXN_50" />
+ <signal name="XLXN_51(31:0)" />
+ <signal name="XLXN_52(31:0)" />
+ <signal name="XLXN_53(26:2)" />
+ <signal name="XLXN_54" />
+ <signal name="XLXN_55" />
+ <signal name="XLXN_56" />
+ <signal name="XLXN_57" />
+ <signal name="XLXN_58" />
+ <signal name="XLXN_59" />
+ <signal name="XLXN_60" />
+ <signal name="XLXN_61(31:0)" />
+ <signal name="XLXN_62(31:0)" />
+ <signal name="XLXN_63(26:2)" />
+ <signal name="XLXN_64" />
+ <signal name="XLXN_65" />
+ <signal name="XLXN_66" />
+ <signal name="XLXN_67" />
+ <signal name="XLXN_68" />
+ <signal name="XLXN_69" />
+ <signal name="XLXN_70" />
+ <signal name="XLXN_71(31:0)" />
+ <signal name="XLXN_72(31:0)" />
+ <signal name="XLXN_73(26:2)" />
+ <signal name="XLXN_74" />
+ <signal name="XLXN_75" />
+ <signal name="XLXN_76" />
+ <signal name="XLXN_77" />
+ <signal name="XLXN_78" />
+ <signal name="XLXN_79" />
+ <signal name="XLXN_80" />
+ <signal name="XLXN_81(31:0)" />
+ <signal name="XLXN_82(31:0)" />
+ <signal name="XLXN_83(26:2)" />
+ <signal name="XLXN_84" />
+ <signal name="XLXN_85" />
+ <signal name="XLXN_86" />
+ <signal name="XLXN_87" />
+ <signal name="XLXN_88" />
+ <signal name="XLXN_89" />
+ <signal name="XLXN_90" />
+ <signal name="XLXN_91(31:0)" />
+ <signal name="XLXN_92(31:0)" />
+ <signal name="XLXN_93(26:2)" />
+ <signal name="XLXN_94" />
+ <signal name="XLXN_95" />
+ <signal name="XLXN_96" />
+ <signal name="XLXN_97" />
+ <signal name="XLXN_98" />
+ <signal name="clk" />
+ <signal name="SPI_MISO" />
+ <signal name="rxd" />
+ <signal name="XLXN_12" />
+ <signal name="XLXN_11" />
+ <signal name="XLXN_121" />
+ <signal name="XLXN_122" />
+ <signal name="XLXN_123(31:0)" />
+ <signal name="XLXN_124(31:0)" />
+ <signal name="XLXN_125(26:2)" />
+ <signal name="XLXN_126" />
+ <signal name="XLXN_127" />
+ <signal name="XLXN_128" />
+ <signal name="XLXN_129" />
+ <signal name="XLXN_130" />
+ <signal name="XLXN_429(31:0)" />
+ <signal name="XLXN_430(31:0)" />
+ <signal name="XLXN_431(26:2)" />
+ <signal name="XLXN_432" />
+ <signal name="XLXN_433" />
+ <signal name="XLXN_434" />
+ <signal name="XLXN_435" />
+ <signal name="XLXN_436" />
+ <signal name="XLXN_437" />
+ <signal name="XLXN_438" />
+ <signal name="WING_AH(7:0)" />
+ <signal name="WING_AL(7:0)" />
+ <signal name="WING_BH(7:0)" />
+ <signal name="WING_BL(7:0)" />
+ <signal name="WING_CH(7:0)" />
+ <signal name="WING_CL(7:0)" />
+ <signal name="XLXN_439" />
+ <signal name="XLXN_440(48:0)" />
+ <signal name="XLXN_441(48:0)" />
+ <signal name="XLXN_442(48:0)" />
+ <signal name="XLXN_443(48:0)" />
+ <signal name="XLXN_444(48:0)" />
+ <signal name="SPI_SCK" />
+ <signal name="SPI_MOSI" />
+ <signal name="TXD" />
+ <signal name="SPI_CS" />
+ <port polarity="Input" name="clk" />
+ <port polarity="Input" name="SPI_MISO" />
+ <port polarity="Input" name="rxd" />
+ <port polarity="BiDirectional" name="WING_AH(7:0)" />
+ <port polarity="BiDirectional" name="WING_AL(7:0)" />
+ <port polarity="BiDirectional" name="WING_BH(7:0)" />
+ <port polarity="BiDirectional" name="WING_BL(7:0)" />
+ <port polarity="BiDirectional" name="WING_CH(7:0)" />
+ <port polarity="BiDirectional" name="WING_CL(7:0)" />
+ <port polarity="Output" name="SPI_SCK" />
+ <port polarity="Output" name="SPI_MOSI" />
+ <port polarity="Output" name="TXD" />
+ <port polarity="BiDirectional" name="SPI_CS" />
+ <blockdef name="zpuino_empty_device">
+ <timestamp>2013-2-8T22:57:48</timestamp>
+ <rect width="152" x="-116" y="112" height="20" />
+ <line x2="-112" y1="96" y2="112" x1="-112" />
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+ <line x2="32" y1="96" y2="112" x1="32" />
+ </blockdef>
+ <blockdef name="ZPUino">
+ <timestamp>2013-2-15T23:47:44</timestamp>
+ <rect width="1752" x="48" y="-588" height="560" />
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+ </blockdef>
+ <blockdef name="Papilio_Default">
+ <timestamp>2013-2-9T1:43:9</timestamp>
+ <rect width="432" x="64" y="-384" height="376" />
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+ <line x2="560" y1="-32" y2="-32" x1="496" />
+ </blockdef>
+ <block symbolname="ZPUino" name="XLXI_26">
+ <blockpin signalname="clk" name="CLK" />
+ <blockpin signalname="SPI_MISO" name="SPI_MISO" />
+ <blockpin signalname="rxd" name="RXD" />
+ <blockpin signalname="XLXN_121" name="wb_clk_i5" />
+ <blockpin signalname="XLXN_122" name="wb_rst_i5" />
+ <blockpin signalname="XLXN_123(31:0)" name="wb_dat_o5(31:0)" />
+ <blockpin signalname="XLXN_124(31:0)" name="wb_dat_i5(31:0)" />
+ <blockpin signalname="XLXN_125(26:2)" name="wb_adr_i5(26:2)" />
+ <blockpin signalname="XLXN_126" name="wb_we_i5" />
+ <blockpin signalname="XLXN_127" name="wb_cyc_i5" />
+ <blockpin signalname="XLXN_128" name="wb_stb_i5" />
+ <blockpin signalname="XLXN_129" name="wb_ack_o5" />
+ <blockpin signalname="XLXN_130" name="wb_inta_o5" />
+ <blockpin signalname="XLXN_11" name="wb_clk_i8" />
+ <blockpin signalname="XLXN_12" name="wb_rst_i8" />
+ <blockpin signalname="XLXN_13(31:0)" name="wb_dat_o8(31:0)" />
+ <blockpin signalname="XLXN_14(31:0)" name="wb_dat_i8(31:0)" />
+ <blockpin signalname="XLXN_15(26:2)" name="wb_adr_i8(26:2)" />
+ <blockpin signalname="XLXN_16" name="wb_we_i8" />
+ <blockpin signalname="XLXN_17" name="wb_cyc_i8" />
+ <blockpin signalname="XLXN_18" name="wb_stb_i8" />
+ <blockpin signalname="XLXN_19" name="wb_ack_o8" />
+ <blockpin signalname="XLXN_20" name="wb_inta_o8" />
+ <blockpin signalname="XLXN_39" name="wb_clk_i9" />
+ <blockpin signalname="XLXN_40" name="wb_rst_i9" />
+ <blockpin signalname="XLXN_41(31:0)" name="wb_dat_o9(31:0)" />
+ <blockpin signalname="XLXN_42(31:0)" name="wb_dat_i9(31:0)" />
+ <blockpin signalname="XLXN_43(26:2)" name="wb_adr_i9(26:2)" />
+ <blockpin signalname="XLXN_44" name="wb_we_i9" />
+ <blockpin signalname="XLXN_45" name="wb_cyc_i9" />
+ <blockpin signalname="XLXN_46" name="wb_stb_i9" />
+ <blockpin signalname="XLXN_47" name="wb_ack_o9" />
+ <blockpin signalname="XLXN_48" name="wb_inta_o9" />
+ <blockpin signalname="XLXN_49" name="wb_clk_i10" />
+ <blockpin signalname="XLXN_50" name="wb_rst_i10" />
+ <blockpin signalname="XLXN_51(31:0)" name="wb_dat_o10(31:0)" />
+ <blockpin signalname="XLXN_52(31:0)" name="wb_dat_i10(31:0)" />
+ <blockpin signalname="XLXN_53(26:2)" name="wb_adr_i10(26:2)" />
+ <blockpin signalname="XLXN_54" name="wb_we_i10" />
+ <blockpin signalname="XLXN_55" name="wb_cyc_i10" />
+ <blockpin signalname="XLXN_56" name="wb_stb_i10" />
+ <blockpin signalname="XLXN_57" name="wb_ack_o10" />
+ <blockpin signalname="XLXN_58" name="wb_inta_o10" />
+ <blockpin signalname="XLXN_59" name="wb_clk_i11" />
+ <blockpin signalname="XLXN_60" name="wb_rst_i11" />
+ <blockpin signalname="XLXN_61(31:0)" name="wb_dat_o11(31:0)" />
+ <blockpin signalname="XLXN_62(31:0)" name="wb_dat_i11(31:0)" />
+ <blockpin signalname="XLXN_63(26:2)" name="wb_adr_i11(26:2)" />
+ <blockpin signalname="XLXN_64" name="wb_we_i11" />
+ <blockpin signalname="XLXN_65" name="wb_cyc_i11" />
+ <blockpin signalname="XLXN_66" name="wb_stb_i11" />
+ <blockpin signalname="XLXN_67" name="wb_ack_o11" />
+ <blockpin signalname="XLXN_68" name="wb_inta_o11" />
+ <blockpin signalname="XLXN_69" name="wb_clk_i12" />
+ <blockpin signalname="XLXN_70" name="wb_rst_i12" />
+ <blockpin signalname="XLXN_71(31:0)" name="wb_dat_o12(31:0)" />
+ <blockpin signalname="XLXN_72(31:0)" name="wb_dat_i12(31:0)" />
+ <blockpin signalname="XLXN_73(26:2)" name="wb_adr_i12(26:2)" />
+ <blockpin signalname="XLXN_74" name="wb_we_i12" />
+ <blockpin signalname="XLXN_75" name="wb_cyc_i12" />
+ <blockpin signalname="XLXN_76" name="wb_stb_i12" />
+ <blockpin signalname="XLXN_77" name="wb_ack_o12" />
+ <blockpin signalname="XLXN_78" name="wb_inta_o12" />
+ <blockpin signalname="XLXN_79" name="wb_clk_i13" />
+ <blockpin signalname="XLXN_80" name="wb_rst_i13" />
+ <blockpin signalname="XLXN_81(31:0)" name="wb_dat_o13(31:0)" />
+ <blockpin signalname="XLXN_82(31:0)" name="wb_dat_i13(31:0)" />
+ <blockpin signalname="XLXN_83(26:2)" name="wb_adr_i13(26:2)" />
+ <blockpin signalname="XLXN_84" name="wb_we_i13" />
+ <blockpin signalname="XLXN_85" name="wb_cyc_i13" />
+ <blockpin signalname="XLXN_86" name="wb_stb_i13" />
+ <blockpin signalname="XLXN_87" name="wb_ack_o13" />
+ <blockpin signalname="XLXN_88" name="wb_inta_o13" />
+ <blockpin signalname="XLXN_89" name="wb_clk_i14" />
+ <blockpin signalname="XLXN_90" name="wb_rst_i14" />
+ <blockpin signalname="XLXN_91(31:0)" name="wb_dat_o14(31:0)" />
+ <blockpin signalname="XLXN_92(31:0)" name="wb_dat_i14(31:0)" />
+ <blockpin signalname="XLXN_93(26:2)" name="wb_adr_i14(26:2)" />
+ <blockpin signalname="XLXN_94" name="wb_we_i14" />
+ <blockpin signalname="XLXN_95" name="wb_cyc_i14" />
+ <blockpin signalname="XLXN_96" name="wb_stb_i14" />
+ <blockpin signalname="XLXN_97" name="wb_ack_o14" />
+ <blockpin signalname="XLXN_98" name="wb_inta_o14" />
+ <blockpin signalname="XLXN_438" name="wb_clk_i15" />
+ <blockpin signalname="XLXN_437" name="wb_rst_i15" />
+ <blockpin signalname="XLXN_429(31:0)" name="wb_dat_o15(31:0)" />
+ <blockpin signalname="XLXN_430(31:0)" name="wb_dat_i15(31:0)" />
+ <blockpin signalname="XLXN_431(26:2)" name="wb_adr_i15(26:2)" />
+ <blockpin signalname="XLXN_432" name="wb_we_i15" />
+ <blockpin signalname="XLXN_433" name="wb_cyc_i15" />
+ <blockpin signalname="XLXN_434" name="wb_stb_i15" />
+ <blockpin signalname="XLXN_435" name="wb_ack_o15" />
+ <blockpin signalname="XLXN_436" name="wb_inta_o15" />
+ <blockpin signalname="SPI_SCK" name="SPI_SCK" />
+ <blockpin signalname="SPI_MOSI" name="SPI_MOSI" />
+ <blockpin signalname="TXD" name="TXD" />
+ <blockpin signalname="SPI_CS" name="SPI_CS" />
+ <blockpin signalname="XLXN_439" name="gpio_clk" />
+ <blockpin signalname="XLXN_441(48:0)" name="gpio_t(48:0)" />
+ <blockpin signalname="XLXN_440(48:0)" name="gpio_o(48:0)" />
+ <blockpin signalname="XLXN_442(48:0)" name="gpio_i(48:0)" />
+ <blockpin signalname="XLXN_443(48:0)" name="gpio_spp_data(48:0)" />
+ <blockpin signalname="XLXN_444(48:0)" name="gpio_spp_read(48:0)" />
+ <blockpin name="v_wb_dat_o(31:0)" />
+ <blockpin name="v_wb_dat_i(31:0)" />
+ <blockpin name="v_wb_adr_i(27:0)" />
+ <blockpin name="v_wb_we_i" />
+ <blockpin name="v_wb_cyc_i" />
+ <blockpin name="v_wb_stb_i" />
+ <blockpin name="v_wb_ack_o" />
+ <blockpin name="vgaclkout" />
+ </block>
+ <block symbolname="Papilio_Default" name="XLXI_32">
+ <blockpin signalname="XLXN_439" name="gpio_clk" />
+ <blockpin signalname="XLXN_440(48:0)" name="gpio_o(48:0)" />
+ <blockpin signalname="XLXN_441(48:0)" name="gpio_t(48:0)" />
+ <blockpin signalname="XLXN_442(48:0)" name="gpio_i(48:0)" />
+ <blockpin signalname="XLXN_443(48:0)" name="gpio_spp_data(48:0)" />
+ <blockpin signalname="XLXN_444(48:0)" name="gpio_spp_read(48:0)" />
+ <blockpin signalname="WING_AH(7:0)" name="WING_AH(7:0)" />
+ <blockpin signalname="WING_AL(7:0)" name="WING_AL(7:0)" />
+ <blockpin signalname="WING_BH(7:0)" name="WING_BH(7:0)" />
+ <blockpin signalname="WING_BL(7:0)" name="WING_BL(7:0)" />
+ <blockpin signalname="WING_CH(7:0)" name="WING_CH(7:0)" />
+ <blockpin signalname="WING_CL(7:0)" name="WING_CL(7:0)" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_15">
+ <blockpin signalname="XLXN_11" name="wb_clk_i" />
+ <blockpin signalname="XLXN_12" name="wb_rst_i" />
+ <blockpin signalname="XLXN_13(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_14(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_15(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_16" name="wb_we_i" />
+ <blockpin signalname="XLXN_17" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_18" name="wb_stb_i" />
+ <blockpin signalname="XLXN_19" name="wb_ack_o" />
+ <blockpin signalname="XLXN_20" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_17">
+ <blockpin signalname="XLXN_49" name="wb_clk_i" />
+ <blockpin signalname="XLXN_50" name="wb_rst_i" />
+ <blockpin signalname="XLXN_51(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_52(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_53(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_54" name="wb_we_i" />
+ <blockpin signalname="XLXN_55" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_56" name="wb_stb_i" />
+ <blockpin signalname="XLXN_57" name="wb_ack_o" />
+ <blockpin signalname="XLXN_58" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_18">
+ <blockpin signalname="XLXN_59" name="wb_clk_i" />
+ <blockpin signalname="XLXN_60" name="wb_rst_i" />
+ <blockpin signalname="XLXN_61(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_62(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_63(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_64" name="wb_we_i" />
+ <blockpin signalname="XLXN_65" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_66" name="wb_stb_i" />
+ <blockpin signalname="XLXN_67" name="wb_ack_o" />
+ <blockpin signalname="XLXN_68" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_19">
+ <blockpin signalname="XLXN_69" name="wb_clk_i" />
+ <blockpin signalname="XLXN_70" name="wb_rst_i" />
+ <blockpin signalname="XLXN_71(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_72(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_73(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_74" name="wb_we_i" />
+ <blockpin signalname="XLXN_75" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_76" name="wb_stb_i" />
+ <blockpin signalname="XLXN_77" name="wb_ack_o" />
+ <blockpin signalname="XLXN_78" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_20">
+ <blockpin signalname="XLXN_79" name="wb_clk_i" />
+ <blockpin signalname="XLXN_80" name="wb_rst_i" />
+ <blockpin signalname="XLXN_81(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_82(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_83(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_84" name="wb_we_i" />
+ <blockpin signalname="XLXN_85" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_86" name="wb_stb_i" />
+ <blockpin signalname="XLXN_87" name="wb_ack_o" />
+ <blockpin signalname="XLXN_88" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_21">
+ <blockpin signalname="XLXN_89" name="wb_clk_i" />
+ <blockpin signalname="XLXN_90" name="wb_rst_i" />
+ <blockpin signalname="XLXN_91(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_92(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_93(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_94" name="wb_we_i" />
+ <blockpin signalname="XLXN_95" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_96" name="wb_stb_i" />
+ <blockpin signalname="XLXN_97" name="wb_ack_o" />
+ <blockpin signalname="XLXN_98" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_31">
+ <blockpin signalname="XLXN_121" name="wb_clk_i" />
+ <blockpin signalname="XLXN_122" name="wb_rst_i" />
+ <blockpin signalname="XLXN_123(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_124(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_125(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_126" name="wb_we_i" />
+ <blockpin signalname="XLXN_127" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_128" name="wb_stb_i" />
+ <blockpin signalname="XLXN_129" name="wb_ack_o" />
+ <blockpin signalname="XLXN_130" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_29">
+ <blockpin signalname="XLXN_39" name="wb_clk_i" />
+ <blockpin signalname="XLXN_40" name="wb_rst_i" />
+ <blockpin signalname="XLXN_41(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_42(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_43(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_44" name="wb_we_i" />
+ <blockpin signalname="XLXN_45" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_46" name="wb_stb_i" />
+ <blockpin signalname="XLXN_47" name="wb_ack_o" />
+ <blockpin signalname="XLXN_48" name="wb_inta_o" />
+ </block>
+ <block symbolname="zpuino_empty_device" name="XLXI_30">
+ <blockpin signalname="XLXN_438" name="wb_clk_i" />
+ <blockpin signalname="XLXN_437" name="wb_rst_i" />
+ <blockpin signalname="XLXN_429(31:0)" name="wb_dat_o(31:0)" />
+ <blockpin signalname="XLXN_430(31:0)" name="wb_dat_i(31:0)" />
+ <blockpin signalname="XLXN_431(26:2)" name="wb_adr_i(26:2)" />
+ <blockpin signalname="XLXN_432" name="wb_we_i" />
+ <blockpin signalname="XLXN_433" name="wb_cyc_i" />
+ <blockpin signalname="XLXN_434" name="wb_stb_i" />
+ <blockpin signalname="XLXN_435" name="wb_ack_o" />
+ <blockpin signalname="XLXN_436" name="wb_inta_o" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="5440" height="3520">
+ <branch name="XLXN_13(31:0)">
+ <wire x2="752" y1="896" y2="928" x1="752" />
+ </branch>
+ <branch name="XLXN_14(31:0)">
+ <wire x2="768" y1="896" y2="928" x1="768" />
+ </branch>
+ <branch name="XLXN_15(26:2)">
+ <wire x2="784" y1="896" y2="928" x1="784" />
+ </branch>
+ <branch name="XLXN_16">
+ <wire x2="800" y1="896" y2="928" x1="800" />
+ </branch>
+ <branch name="XLXN_17">
+ <wire x2="816" y1="896" y2="928" x1="816" />
+ </branch>
+ <branch name="XLXN_18">
+ <wire x2="832" y1="896" y2="928" x1="832" />
+ </branch>
+ <branch name="XLXN_19">
+ <wire x2="848" y1="896" y2="928" x1="848" />
+ </branch>
+ <branch name="XLXN_20">
+ <wire x2="864" y1="896" y2="928" x1="864" />
+ </branch>
+ <branch name="XLXN_39">
+ <wire x2="896" y1="896" y2="928" x1="896" />
+ </branch>
+ <branch name="XLXN_40">
+ <wire x2="912" y1="896" y2="928" x1="912" />
+ </branch>
+ <branch name="XLXN_41(31:0)">
+ <wire x2="928" y1="896" y2="928" x1="928" />
+ </branch>
+ <branch name="XLXN_42(31:0)">
+ <wire x2="944" y1="896" y2="928" x1="944" />
+ </branch>
+ <branch name="XLXN_43(26:2)">
+ <wire x2="960" y1="896" y2="928" x1="960" />
+ </branch>
+ <branch name="XLXN_44">
+ <wire x2="976" y1="896" y2="928" x1="976" />
+ </branch>
+ <branch name="XLXN_45">
+ <wire x2="992" y1="896" y2="928" x1="992" />
+ </branch>
+ <branch name="XLXN_46">
+ <wire x2="1008" y1="896" y2="928" x1="1008" />
+ </branch>
+ <branch name="XLXN_47">
+ <wire x2="1024" y1="896" y2="928" x1="1024" />
+ </branch>
+ <branch name="XLXN_48">
+ <wire x2="1040" y1="896" y2="928" x1="1040" />
+ </branch>
+ <branch name="XLXN_49">
+ <wire x2="1072" y1="896" y2="928" x1="1072" />
+ </branch>
+ <branch name="XLXN_50">
+ <wire x2="1088" y1="896" y2="928" x1="1088" />
+ </branch>
+ <branch name="XLXN_51(31:0)">
+ <wire x2="1104" y1="896" y2="928" x1="1104" />
+ </branch>
+ <branch name="XLXN_52(31:0)">
+ <wire x2="1120" y1="896" y2="928" x1="1120" />
+ </branch>
+ <branch name="XLXN_53(26:2)">
+ <wire x2="1136" y1="896" y2="928" x1="1136" />
+ </branch>
+ <branch name="XLXN_54">
+ <wire x2="1152" y1="896" y2="928" x1="1152" />
+ </branch>
+ <branch name="XLXN_55">
+ <wire x2="1168" y1="896" y2="928" x1="1168" />
+ </branch>
+ <branch name="XLXN_56">
+ <wire x2="1184" y1="896" y2="928" x1="1184" />
+ </branch>
+ <branch name="XLXN_57">
+ <wire x2="1200" y1="896" y2="928" x1="1200" />
+ </branch>
+ <branch name="XLXN_58">
+ <wire x2="1216" y1="896" y2="928" x1="1216" />
+ </branch>
+ <branch name="XLXN_59">
+ <wire x2="1248" y1="896" y2="928" x1="1248" />
+ </branch>
+ <branch name="XLXN_60">
+ <wire x2="1264" y1="896" y2="928" x1="1264" />
+ </branch>
+ <branch name="XLXN_61(31:0)">
+ <wire x2="1280" y1="896" y2="928" x1="1280" />
+ </branch>
+ <branch name="XLXN_62(31:0)">
+ <wire x2="1296" y1="896" y2="928" x1="1296" />
+ </branch>
+ <branch name="XLXN_63(26:2)">
+ <wire x2="1312" y1="896" y2="928" x1="1312" />
+ </branch>
+ <branch name="XLXN_64">
+ <wire x2="1328" y1="896" y2="928" x1="1328" />
+ </branch>
+ <branch name="XLXN_65">
+ <wire x2="1344" y1="896" y2="928" x1="1344" />
+ </branch>
+ <branch name="XLXN_66">
+ <wire x2="1360" y1="896" y2="928" x1="1360" />
+ </branch>
+ <branch name="XLXN_67">
+ <wire x2="1376" y1="896" y2="928" x1="1376" />
+ </branch>
+ <branch name="XLXN_68">
+ <wire x2="1392" y1="896" y2="928" x1="1392" />
+ </branch>
+ <branch name="XLXN_69">
+ <wire x2="1424" y1="896" y2="928" x1="1424" />
+ </branch>
+ <branch name="XLXN_70">
+ <wire x2="1440" y1="896" y2="928" x1="1440" />
+ </branch>
+ <branch name="XLXN_71(31:0)">
+ <wire x2="1456" y1="896" y2="928" x1="1456" />
+ </branch>
+ <branch name="XLXN_72(31:0)">
+ <wire x2="1472" y1="896" y2="928" x1="1472" />
+ </branch>
+ <branch name="XLXN_73(26:2)">
+ <wire x2="1488" y1="896" y2="928" x1="1488" />
+ </branch>
+ <branch name="XLXN_74">
+ <wire x2="1504" y1="896" y2="928" x1="1504" />
+ </branch>
+ <branch name="XLXN_75">
+ <wire x2="1520" y1="896" y2="928" x1="1520" />
+ </branch>
+ <branch name="XLXN_76">
+ <wire x2="1536" y1="896" y2="928" x1="1536" />
+ </branch>
+ <branch name="XLXN_77">
+ <wire x2="1552" y1="896" y2="928" x1="1552" />
+ </branch>
+ <branch name="XLXN_78">
+ <wire x2="1568" y1="896" y2="928" x1="1568" />
+ </branch>
+ <branch name="XLXN_79">
+ <wire x2="1600" y1="896" y2="928" x1="1600" />
+ </branch>
+ <branch name="XLXN_80">
+ <wire x2="1616" y1="896" y2="928" x1="1616" />
+ </branch>
+ <branch name="XLXN_81(31:0)">
+ <wire x2="1632" y1="896" y2="928" x1="1632" />
+ </branch>
+ <branch name="XLXN_82(31:0)">
+ <wire x2="1648" y1="896" y2="928" x1="1648" />
+ </branch>
+ <branch name="XLXN_83(26:2)">
+ <wire x2="1664" y1="896" y2="928" x1="1664" />
+ </branch>
+ <branch name="XLXN_84">
+ <wire x2="1680" y1="896" y2="928" x1="1680" />
+ </branch>
+ <branch name="XLXN_85">
+ <wire x2="1696" y1="896" y2="928" x1="1696" />
+ </branch>
+ <branch name="XLXN_86">
+ <wire x2="1712" y1="896" y2="928" x1="1712" />
+ </branch>
+ <branch name="XLXN_87">
+ <wire x2="1728" y1="896" y2="928" x1="1728" />
+ </branch>
+ <branch name="XLXN_88">
+ <wire x2="1744" y1="896" y2="928" x1="1744" />
+ </branch>
+ <branch name="XLXN_89">
+ <wire x2="1776" y1="896" y2="928" x1="1776" />
+ </branch>
+ <branch name="XLXN_90">
+ <wire x2="1792" y1="896" y2="928" x1="1792" />
+ </branch>
+ <branch name="XLXN_91(31:0)">
+ <wire x2="1808" y1="896" y2="928" x1="1808" />
+ </branch>
+ <branch name="XLXN_92(31:0)">
+ <wire x2="1824" y1="896" y2="928" x1="1824" />
+ </branch>
+ <branch name="XLXN_93(26:2)">
+ <wire x2="1840" y1="896" y2="928" x1="1840" />
+ </branch>
+ <branch name="XLXN_94">
+ <wire x2="1856" y1="896" y2="928" x1="1856" />
+ </branch>
+ <branch name="XLXN_95">
+ <wire x2="1872" y1="896" y2="928" x1="1872" />
+ </branch>
+ <branch name="XLXN_96">
+ <wire x2="1888" y1="896" y2="928" x1="1888" />
+ </branch>
+ <branch name="XLXN_97">
+ <wire x2="1904" y1="896" y2="928" x1="1904" />
+ </branch>
+ <branch name="XLXN_98">
+ <wire x2="1920" y1="896" y2="928" x1="1920" />
+ </branch>
+ <branch name="clk">
+ <wire x2="464" y1="384" y2="384" x1="432" />
+ </branch>
+ <branch name="SPI_MISO">
+ <wire x2="464" y1="448" y2="448" x1="432" />
+ </branch>
+ <branch name="rxd">
+ <wire x2="464" y1="512" y2="512" x1="432" />
+ </branch>
+ <branch name="XLXN_12">
+ <wire x2="736" y1="896" y2="928" x1="736" />
+ </branch>
+ <branch name="XLXN_11">
+ <wire x2="720" y1="896" y2="928" x1="720" />
+ </branch>
+ <branch name="XLXN_121">
+ <wire x2="544" y1="896" y2="928" x1="544" />
+ </branch>
+ <branch name="XLXN_122">
+ <wire x2="560" y1="896" y2="928" x1="560" />
+ </branch>
+ <branch name="XLXN_123(31:0)">
+ <wire x2="576" y1="896" y2="928" x1="576" />
+ </branch>
+ <branch name="XLXN_124(31:0)">
+ <wire x2="592" y1="896" y2="928" x1="592" />
+ </branch>
+ <branch name="XLXN_125(26:2)">
+ <wire x2="608" y1="896" y2="928" x1="608" />
+ </branch>
+ <branch name="XLXN_126">
+ <wire x2="624" y1="896" y2="928" x1="624" />
+ </branch>
+ <branch name="XLXN_127">
+ <wire x2="640" y1="896" y2="928" x1="640" />
+ </branch>
+ <branch name="XLXN_128">
+ <wire x2="656" y1="896" y2="928" x1="656" />
+ </branch>
+ <branch name="XLXN_129">
+ <wire x2="672" y1="896" y2="928" x1="672" />
+ </branch>
+ <branch name="XLXN_130">
+ <wire x2="688" y1="896" y2="928" x1="688" />
+ </branch>
+ <iomarker fontsize="28" x="432" y="384" name="clk" orien="R180" />
+ <iomarker fontsize="28" x="432" y="448" name="SPI_MISO" orien="R180" />
+ <iomarker fontsize="28" x="432" y="512" name="rxd" orien="R180" />
+ <instance x="480" y="896" name="XLXI_26" orien="R0">
+ </instance>
+ <branch name="XLXN_429(31:0)">
+ <wire x2="1984" y1="896" y2="928" x1="1984" />
+ </branch>
+ <branch name="XLXN_430(31:0)">
+ <wire x2="2000" y1="896" y2="928" x1="2000" />
+ </branch>
+ <branch name="XLXN_431(26:2)">
+ <wire x2="2016" y1="896" y2="928" x1="2016" />
+ </branch>
+ <branch name="XLXN_432">
+ <wire x2="2032" y1="896" y2="928" x1="2032" />
+ </branch>
+ <branch name="XLXN_433">
+ <wire x2="2048" y1="896" y2="928" x1="2048" />
+ </branch>
+ <branch name="XLXN_434">
+ <wire x2="2064" y1="896" y2="928" x1="2064" />
+ </branch>
+ <branch name="XLXN_435">
+ <wire x2="2080" y1="896" y2="928" x1="2080" />
+ </branch>
+ <branch name="XLXN_436">
+ <wire x2="2096" y1="896" y2="928" x1="2096" />
+ </branch>
+ <branch name="XLXN_437">
+ <wire x2="1968" y1="896" y2="928" x1="1968" />
+ </branch>
+ <branch name="XLXN_438">
+ <wire x2="1952" y1="896" y2="928" x1="1952" />
+ </branch>
+ <branch name="WING_AH(7:0)">
+ <wire x2="3168" y1="592" y2="592" x1="3152" />
+ <wire x2="3184" y1="592" y2="592" x1="3168" />
+ </branch>
+ <branch name="WING_AL(7:0)">
+ <wire x2="3168" y1="656" y2="656" x1="3152" />
+ <wire x2="3184" y1="656" y2="656" x1="3168" />
+ </branch>
+ <branch name="WING_BH(7:0)">
+ <wire x2="3168" y1="720" y2="720" x1="3152" />
+ <wire x2="3184" y1="720" y2="720" x1="3168" />
+ </branch>
+ <branch name="WING_BL(7:0)">
+ <wire x2="3168" y1="784" y2="784" x1="3152" />
+ <wire x2="3184" y1="784" y2="784" x1="3168" />
+ </branch>
+ <branch name="WING_CH(7:0)">
+ <wire x2="3168" y1="848" y2="848" x1="3152" />
+ <wire x2="3184" y1="848" y2="848" x1="3168" />
+ </branch>
+ <branch name="WING_CL(7:0)">
+ <wire x2="3168" y1="912" y2="912" x1="3152" />
+ <wire x2="3184" y1="912" y2="912" x1="3168" />
+ </branch>
+ <iomarker fontsize="28" x="3184" y="592" name="WING_AH(7:0)" orien="R0" />
+ <iomarker fontsize="28" x="3184" y="656" name="WING_AL(7:0)" orien="R0" />
+ <iomarker fontsize="28" x="3184" y="720" name="WING_BH(7:0)" orien="R0" />
+ <iomarker fontsize="28" x="3184" y="784" name="WING_BL(7:0)" orien="R0" />
+ <iomarker fontsize="28" x="3184" y="848" name="WING_CH(7:0)" orien="R0" />
+ <iomarker fontsize="28" x="3184" y="912" name="WING_CL(7:0)" orien="R0" />
+ <instance x="2592" y="944" name="XLXI_32" orien="R0">
+ </instance>
+ <branch name="XLXN_439">
+ <wire x2="2592" y1="592" y2="592" x1="2336" />
+ </branch>
+ <branch name="XLXN_440(48:0)">
+ <wire x2="2592" y1="624" y2="624" x1="2336" />
+ </branch>
+ <branch name="XLXN_441(48:0)">
+ <wire x2="2592" y1="656" y2="656" x1="2336" />
+ </branch>
+ <branch name="XLXN_442(48:0)">
+ <wire x2="2592" y1="688" y2="688" x1="2336" />
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+ </branch>
+ <branch name="XLXN_444(48:0)">
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+ </branch>
+ <branch name="SPI_SCK">
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+ </branch>
+ <iomarker fontsize="28" x="2368" y="336" name="SPI_SCK" orien="R0" />
+ <branch name="SPI_MOSI">
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+ </branch>
+ <iomarker fontsize="28" x="2368" y="400" name="SPI_MOSI" orien="R0" />
+ <branch name="TXD">
+ <wire x2="2368" y1="464" y2="464" x1="2336" />
+ </branch>
+ <iomarker fontsize="28" x="2368" y="464" name="TXD" orien="R0" />
+ <branch name="SPI_CS">
+ <wire x2="2368" y1="528" y2="528" x1="2336" />
+ </branch>
+ <iomarker fontsize="28" x="2368" y="528" name="SPI_CS" orien="R0" />
+ <instance x="832" y="832" name="XLXI_15" orien="R0">
+ </instance>
+ <instance x="1184" y="832" name="XLXI_17" orien="R0">
+ </instance>
+ <instance x="1360" y="832" name="XLXI_18" orien="R0">
+ </instance>
+ <instance x="1536" y="832" name="XLXI_19" orien="R0">
+ </instance>
+ <instance x="1712" y="832" name="XLXI_20" orien="R0">
+ </instance>
+ <instance x="1888" y="832" name="XLXI_21" orien="R0">
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+ <instance x="656" y="832" name="XLXI_31" orien="R0">
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+ <instance x="1008" y="832" name="XLXI_29" orien="R0">
+ </instance>
+ <instance x="2064" y="832" name="XLXI_30" orien="R0">
+ </instance>
+ </sheet>
+</drawing>
View
565 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/Papilio_SOC_Base.xise
@@ -0,0 +1,565 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="Papilio_SOC_Base.sch" xil_pn:type="FILE_SCHEMATIC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+ </file>
+ <file xil_pn:name="papilio_one.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_empty_device.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/prom-generic-dp-32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/zpuino.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/prescaler.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/shifter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/spiclkgen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/timer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/uart_brgen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/wbarb2_1.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/wbmux2.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/wishbonepkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpu_core_extreme.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_crc16.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_debug_core.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_gpio.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_intr.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_io.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_serialreset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
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+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_timers.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
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+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_top.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_uart.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_uart_mv_filter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_uart_rx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuinopkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpupkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/clkgen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/variants/papilio_soc/zpu_config.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/zpuino_config.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/tx_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/pad.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/wb_rom_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/boards/papilio_one/s3e500/stack.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/dualport_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/vga_zxspectrum.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/gh_vhdl_lib/memory/gh_fifo_async_rrd_sr_wf.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/gh_vhdl_lib/memory/gh_sram_1wp_2rp_sc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/gh_vhdl_lib/custom_MSI/gh_binary2gray.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/gh_vhdl_lib/custom_MSI/gh_gray2binary.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_sigmadelta.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/zpuino_sevenseg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../zpu/hdl/zpuino/contrib/zpuino_YM2149_linmix.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/contrib/NetSID/src/sid_6581.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/contrib/i2c/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="../../../zpu/hdl/zpuino/contrib/papilio_stepper/papilio_stepper.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../hardware/Papilio_Default.vhd" xil_pn:type="FILE_VHDL">
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+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="Papilio_SOC_Base" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-04T16:52:44" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0BF1410E9CA045EFA8E8B9B45DA92BD1" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
View
271 Papilio_SOC_Schematic/example_SOCs/papilio_one_250k_base/ZPUino.sym
@@ -0,0 +1,271 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="ZPUino">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2013-2-15T23:47:44</timestamp>
+ <pin polarity="Input" x="-16" y="-512" name="CLK" />
+ <pin polarity="Input" x="-16" y="-448" name="SPI_MISO" />
+ <pin polarity="Input" x="-16" y="-384" name="RXD" />
+ <pin polarity="Output" x="64" y="0" name="wb_clk_i5" />
+ <pin polarity="Output" x="80" y="0" name="wb_rst_i5" />
+ <pin polarity="Input" x="96" y="0" name="wb_dat_o5(31:0)" />
+ <pin polarity="Output" x="112" y="0" name="wb_dat_i5(31:0)" />
+ <pin polarity="Output" x="128" y="0" name="wb_adr_i5(26:2)" />
+ <pin polarity="Output" x="144" y="0" name="wb_we_i5" />
+ <pin polarity="Output" x="160" y="0" name="wb_cyc_i5" />
+ <pin polarity="Output" x="176" y="0" name="wb_stb_i5" />
+ <pin polarity="Input" x="192" y="0" name="wb_ack_o5" />
+ <pin polarity="Input" x="208" y="0" name="wb_inta_o5" />
+ <pin polarity="Output" x="240" y="0" name="wb_clk_i8" />
+ <pin polarity="Output" x="256" y="0" name="wb_rst_i8" />
+ <pin polarity="Input" x="272" y="0" name="wb_dat_o8(31:0)" />
+ <pin polarity="Output" x="288" y="0" name="wb_dat_i8(31:0)" />
+ <pin polarity="Output" x="304" y="0" name="wb_adr_i8(26:2)" />
+ <pin polarity="Output" x="320" y="0" name="wb_we_i8" />
+ <pin polarity="Output" x="336" y="0" name="wb_cyc_i8" />
+ <pin polarity="Output" x="352" y="0" name="wb_stb_i8" />
+ <pin polarity="Input" x="368" y="0" name="wb_ack_o8" />
+ <pin polarity="Input" x="384" y="0" name="wb_inta_o8" />
+ <pin polarity="Output" x="416" y="0" name="wb_clk_i9" />
+ <pin polarity="Output" x="432" y="0" name="wb_rst_i9" />
+ <pin polarity="Input" x="448" y="0" name="wb_dat_o9(31:0)" />
+ <pin polarity="Output" x="464" y="0" name="wb_dat_i9(31:0)" />
+ <pin polarity="Output" x="480" y="0" name="wb_adr_i9(26:2)" />
+ <pin polarity="Output" x="496" y="0" name="wb_we_i9" />
+ <pin polarity="Output" x="512" y="0" name="wb_cyc_i9" />
+ <pin polarity="Output" x="528" y="0" name="wb_stb_i9" />
+ <pin polarity="Input" x="544" y="0" name="wb_ack_o9" />
+ <pin polarity="Input" x="560" y="0" name="wb_inta_o9" />
+ <pin polarity="Output" x="592" y="0" name="wb_clk_i10" />
+ <pin polarity="Output" x="608" y="0" name="wb_rst_i10" />
+ <pin polarity="Input" x="624" y="0" name="wb_dat_o10(31:0)" />
+ <pin polarity="Output" x="640" y="0" name="wb_dat_i10(31:0)" />
+ <pin polarity="Output" x="656" y="0" name="wb_adr_i10(26:2)" />
+ <pin polarity="Output" x="672" y="0" name="wb_we_i10" />
+ <pin polarity="Output" x="688" y="0" name="wb_cyc_i10" />
+ <pin polarity="Output" x="704" y="0" name="wb_stb_i10" />
+ <pin polarity="Input" x="720" y="0" name="wb_ack_o10" />
+ <pin polarity="Input" x="736" y="0" name="wb_inta_o10" />
+ <pin polarity="Output" x="768" y="0" name="wb_clk_i11" />
+ <pin polarity="Output" x="784" y="0" name="wb_rst_i11" />
+ <pin polarity="Input" x="800" y="0" name="wb_dat_o11(31:0)" />