GenMul (version 1)
GenMul is a multiplier generator which outputs multiplier circuits in Verilog. The input size of a multiplier and each multiplier stage can be configured with GenMul. For more information visit www.sca-verification.org. There you can also run GenMul via Browser.
Clone GenMul using:
git clone https://github.com/amahzoon/genmul.git
Installation (shell interface)
To build GenMul binary:
mkdir build cd build cmake .. make install -j2
After installation, GenMul can be run from
mkdir build cd build emconfigure cmake .. emmake make install -j2
The compiled files are accessible through
After running, GenMul asks you to choose the architectures for the Partial Product Generator (PPG), Partial Product Accumulator (PPA), and Final Stage Adder (FSA), respectively. Then, the bit sizes of the first and second inputs have to be set. Finally, the Verilog file of the multiplier is generated.