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COS Report.pdf | ||
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LCD.vhd | ||
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LICENSE | ||
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README.md | ||
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integrtn_mem.vhd | ||
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memory.vhd | ||
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processor.vhd | ||
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register.vhd | ||
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subset.vhd | ||
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test_bench.vhd | ||
32 bit RISC Microprocessor in VHDL language and implemented on Altera FPGA.
The Test bench module is executed in the model-sim software and the LCD module is implemented on the FPGA to display the Register value, Memory value and the Program counter.