csr.wishbone: fix WishboneCSRBridge cycle counter.

[jfng]

Before this commit, a CSR could be read two times in a single WB transaction.

Repro:

from nmigen import *
from nmigen.back.pysim import *

from nmigen_soc import csr
from nmigen_soc.memory import MemoryMap
from nmigen_soc.csr.wishbone import WishboneCSRBridge


csr_bus = csr.Interface(addr_width=2, data_width=8)
csr_bus.memory_map = MemoryMap(addr_width=2, data_width=8)

dut = WishboneCSRBridge(csr_bus, data_width=32)

def process():
    yield dut.wb_bus.adr.eq(0x0)
    yield dut.wb_bus.cyc.eq(1)
    yield dut.wb_bus.stb.eq(1)
    yield dut.wb_bus.sel.eq(0b0001)
    yield
    while not (yield dut.wb_bus.ack):
        yield
    yield dut.wb_bus.cyc.eq(0)
    yield dut.wb_bus.stb.eq(0)

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
with sim.write_vcd("repro.vcd"):
    sim.run()

After this commit, only one read occurs:

[codecov]

Codecov Report

Merging #13 into master will not change coverage by %.
The diff coverage is 100.00%.

@@           Coverage Diff           @@
##           master      #13   +/-   ##
=======================================
  Coverage   99.63%   99.63%           
=======================================
  Files           4        4           
  Lines         552      552           
  Branches      127      127           
=======================================
  Hits          550      550           
  Misses          1        1           
  Partials        1        1           

Impacted Files	Coverage Δ
nmigen_soc/csr/wishbone.py	100.00% <100.00%> (ø)

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[whitequark]

Thanks. If it's not hard, could you add a test?

[jfng]

Done, I think. I believe that the bug was able to hide because the test suite deasserted STB on the same cycle as ACK, instead of 1 cycle later. See: