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[WIP]wishbone.Connector class #21

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@Fatsie Fatsie commented Jul 1, 2020

Currently pull request as WIP:

  • First code for review
  • Further discussion in #18 on feature set of class
  • Connecting initiator bus with data width greater than data width of subordinate bus is not implemented. Would PR be acceptable without this implementation ?
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@codecov codecov bot commented Jul 1, 2020

Codecov Report

Merging #21 (ec94f31) into master (c754caf) will not change coverage.
The diff coverage is 100.00%.

Current head ec94f31 differs from pull request most recent head 3db2a83. Consider uploading reports for the commit 3db2a83 to get more accurate results
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@@            Coverage Diff            @@
##            master       #21   +/-   ##
=========================================
  Coverage   100.00%   100.00%           
=========================================
  Files            7         6    -1     
  Lines          693       725   +32     
  Branches       145       160   +15     
=========================================
+ Hits           693       725   +32     
Impacted Files Coverage Δ
nmigen_soc/wishbone/bus.py 100.00% <100.00%> (ø)
nmigen_soc/periph.py

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@Fatsie
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@Fatsie Fatsie commented Jul 1, 2020

* Connecting initiator bus with data width greater than data width of subordinate bus is not implemented. Would PR be acceptable without this implementation ?

Reason I ask is that I don't need this feature for my use case and implementation of it may take some time.

@whitequark whitequark requested a review from jfng Jul 1, 2020
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@whitequark whitequark commented Jul 1, 2020

Reason I ask is that I don't need this feature for my use case and implementation of it may take some time.

In general my preference is to have a complete solution even if it takes a bit longer, but let's get the review started before you put more time into that.

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@jfng jfng left a comment

We should also add support for memory maps. If the subordinate bus has a memory map, it should be exposed to the initiator bus. Something like this:

try:
    sub_map  = sub_bus.memory_map
    intr_map = MemoryMap(...)
    intr_map.add_window(sub_map, addr=0, sparse=False)
    self.intr_bus.memory_map = intr_map
except NotImplementedError:
    # Subordinate bus does not have a memory map.
    pass

nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
@@ -166,6 +167,147 @@ def memory_map(self, memory_map):
self._map = memory_map


class Connector(Elaboratable):
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@jfng jfng Jul 6, 2020

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Connector seems too generic for a width up-converter. How about Upconverter ?

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@Fatsie Fatsie Jul 7, 2020

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As discussed in #18 I did use Connector because the functionality is broader then upconverting, it's functionality is to connect a single initiator to a single subordinate. Upconverting will be done when necessary.
You will need to agree with @whitequark what to go for.

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@jfng jfng Jul 8, 2020

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Could the Connector class be composed internally of two separate up- and down-converter classes ?

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@Fatsie Fatsie Jul 8, 2020

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I can see during implementation of the feature if it makes sense to do that but current feeling is that it will cause unnecessary code duplication with negligible improvement in code clarity or maintainability.

nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
raise NotImplementedError(
"Support for multi-cycle bus operation when initiator data_width is"
"bigger than the subordinate one is not implemented."
)
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@jfng jfng Jul 6, 2020

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This should be a ValueError.

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@Fatsie Fatsie Jul 7, 2020

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Plan is to later also implement downsizing in this class therefor NotImlementedError. This is thus alsot related to discussion in #18.

nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved
nmigen_soc/wishbone/bus.py Outdated Show resolved Hide resolved

m = Module()

common_addr_width = min(intr_bus.addr_width, sub_bus.addr_width)
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@jfng jfng Jul 6, 2020

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Could this be simplified to sub_bus.addr_width ? intr_bus.addr_width >= sub_bus.addr_width is asserted later is the code.

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@Fatsie Fatsie Jul 7, 2020

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I removed the assert now, it was planned to be removed if multi-cycle bus was implemented.
Kept the common_addr_width definition as it is already future proof.

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@Fatsie Fatsie commented Jul 7, 2020

We should also add support for memory maps. If the subordinate bus has a memory map, it should be exposed to the initiator bus. Something like this:

try:
    sub_map  = sub_bus.memory_map
    intr_map = MemoryMap(...)
    intr_map.add_window(sub_map, addr=0, sparse=False)
    self.intr_bus.memory_map = intr_map
except NotImplementedError:
    # Subordinate bus does not have a memory map.
    pass

Actually in the first version I even enforced a memory map on subordinate bus like the Decoder does. But I removed all memory map code after I got problems with the unit test for different granularity. I based the data_width of the memory maps on the granularity of each bus. Then you get an error when adding the subordinate memorymap to the initiator one due to different data_width.

@Fatsie Fatsie force-pushed the wishbone_connector branch from 280890c to ec94f31 Jul 7, 2020
Implementation of a module that allows to connect one initiator to one
subordinate.bus. Currently connecting initiator bus with data width
greater than the subordinate bus is not implemented. Implementation
of that feature will need to instantiate multiple subordinate bus cycles
for one initiator bus cycle.
@Fatsie Fatsie force-pushed the wishbone_connector branch from ec94f31 to 3db2a83 Apr 20, 2021
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