From 7dcd3d37ff901b00cee5e83e6b84fe1ca21e7d61 Mon Sep 17 00:00:00 2001
From: Irides <irides@irides.network>
Date: Wed, 15 Dec 2021 19:47:48 -0600
Subject: [PATCH] sim.pysim: use "bench" as a top level root for testbench
 signals.

Fixes #561.
---
 amaranth/sim/pysim.py | 4 ++--
 docs/changes.rst      | 1 +
 tests/test_sim.py     | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py
index a295d56ca..504361dd7 100644
--- a/amaranth/sim/pysim.py
+++ b/amaranth/sim/pysim.py
@@ -19,7 +19,7 @@ class _NameExtractor:
     def __init__(self):
         self.names = SignalDict()
 
-    def __call__(self, fragment, *, hierarchy=("top",)):
+    def __call__(self, fragment, *, hierarchy=("bench", "top",)):
         def add_signal_name(signal):
             hierarchical_signal_name = (*hierarchy, signal.name)
             if signal not in self.names:
@@ -74,7 +74,7 @@ def __init__(self, fragment, *, vcd_file, gtkw_file=None, traces=()):
         trace_names = SignalDict()
         for trace in traces:
             if trace not in signal_names:
-                trace_names[trace] = {("top", trace.name)}
+                trace_names[trace] = {('bench', trace.name)}
             self.traces.append(trace)
 
         if self.vcd_writer is None:
diff --git a/docs/changes.rst b/docs/changes.rst
index 7c481878d..74e2d9fda 100644
--- a/docs/changes.rst
+++ b/docs/changes.rst
@@ -70,6 +70,7 @@ Toolchain changes
 * Added: :meth:`build.BuildPlan.execute_remote_ssh`.
 * Deprecated: :class:`test.utils.FHDLTestCase`, with no replacement.
 * Deprecated: :func:`back.rtlil.convert()` and :func:`back.verilog.convert()` without an explicit `ports=` argument.
+* Changed: VCD output now uses a top-level "bench" module that contains testbench only signals.
 
 
 Platform integration changes
diff --git a/tests/test_sim.py b/tests/test_sim.py
index c12b0871a..e8ffa5d57 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -849,7 +849,7 @@ def test_bug_595(self):
                 pass
         sim = Simulator(dut)
         with self.assertRaisesRegex(NameError,
-                r"^Signal 'top\.name with space_state' contains a whitespace character$"):
+                r"^Signal 'bench\.top\.name with space_state' contains a whitespace character$"):
             with open(os.path.devnull, "w") as f:
                 with sim.write_vcd(f):
                     sim.run()