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build,vendor: never carry around parts of differential signals.
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
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whitequark and Jean THOMAS committed Jul 31, 2020
1 parent 07dc163 commit 83e5aa769c7d1fbe34598f869b0c7cf40d90a4e3
@@ -148,16 +148,15 @@ def add_pin_fragment(pin, pin_fragment):
if pin.dir == "io":
add_pin_fragment(pin, self.get_input_output(pin, port, attrs, invert))

for pin, p_port, n_port, attrs, invert in self.iter_differential_pins():
for pin, port, attrs, invert in self.iter_differential_pins():
if pin.dir == "i":
add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input(pin, port, attrs, invert))
if pin.dir == "o":
add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_output(pin, port, attrs, invert))
if pin.dir == "oe":
add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_tristate(pin, port, attrs, invert))
if pin.dir == "io":
add_pin_fragment(pin,
self.get_diff_input_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))

fragment._propagate_ports(ports=self.iter_ports(), all_undef_as_ports=False)
return self.toolchain_prepare(fragment, name, **kwargs)
@@ -239,19 +238,19 @@ def get_input_output(self, pin, port, attrs, invert):
m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(), valid_attrs=None)

@@ -128,9 +128,15 @@ def resolve(resource, dir, xdr, name, attrs):
phys_names = phys.names
port = Record([("io", len(phys))], name=name)
if isinstance(phys, DiffPairs):
phys_names = phys.p.names + phys.n.names
port = Record([("p", len(phys)),
("n", len(phys))], name=name)
phys_names = []
record_fields = []
if not self.should_skip_port_component(None, attrs, "p"):
phys_names += phys.p.names
record_fields.append(("p", len(phys)))
if not self.should_skip_port_component(None, attrs, "n"):
phys_names += phys.n.names
record_fields.append(("n", len(phys)))
port = Record(record_fields, name=name)
if dir == "-":
pin = None
else:
@@ -248,7 +248,7 @@ def get_input(self, pin, port, attrs, invert):
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="FALSE",
i_datain=port,
i_datain=port.io,
o_dataout=self._get_ireg(m, pin, invert)
)
return m
@@ -266,7 +266,7 @@ def get_output(self, pin, port, attrs, invert):
p_use_differential_mode="FALSE",
p_use_oe="FALSE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=port,
o_dataout=port.io,
)
return m

@@ -283,7 +283,7 @@ def get_tristate(self, pin, port, attrs, invert):
p_use_differential_mode="FALSE",
p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=port,
o_dataout=port.io,
i_oe=self._get_oereg(m, pin)
)
return m
@@ -300,36 +300,36 @@ def get_input_output(self, pin, port, attrs, invert):
p_number_of_channels=pin.width,
p_use_differential_mode="FALSE",
i_datain=self._get_oreg(m, pin, invert),
io_dataio=port,
io_dataio=port.io,
o_dataout=self._get_ireg(m, pin, invert),
i_oe=self._get_oereg(m, pin),
)
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_in",
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="TRUE",
i_datain=p_port,
i_datain_b=n_port,
i_datain=port.p,
i_datain_b=port.n,
o_dataout=self._get_ireg(m, pin, invert)
)
return m

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_out",
@@ -338,17 +338,17 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
p_use_differential_mode="TRUE",
p_use_oe="FALSE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=p_port,
o_dataout_b=n_port,
o_dataout=port.p,
o_dataout_b=port.n,
)
return m

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_out",
@@ -357,27 +357,27 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
p_use_differential_mode="TRUE",
p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=p_port,
o_dataout_b=n_port,
o_dataout=port.p,
o_dataout_b=port.n,
i_oe=self._get_oereg(m, pin),
)
return m

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_bidir",
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="TRUE",
i_datain=self._get_oreg(m, pin, invert),
io_dataio=p_port,
io_dataio_b=n_port,
io_dataio=port.p,
io_dataio_b=port.n,
o_dataout=self._get_ireg(m, pin, invert),
i_oe=self._get_oereg(m, pin),
)
@@ -553,9 +553,9 @@ def get_input(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=port[bit],
i_I=port.io[bit],
o_O=i[bit]
)
return m
@@ -565,10 +565,10 @@ def get_output(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=port[bit]
o_O=port.io[bit]
)
return m

@@ -577,11 +577,11 @@ def get_tristate(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port[bit]
o_O=port.io[bit]
)
return m

@@ -590,63 +590,63 @@ def get_input_output(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_B=port[bit]
io_B=port.io[bit]
)
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=p_port[bit],
i_I=p_port.io[bit],
o_O=i[bit]
)
return m

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=p_port[bit],
o_O=port.p[bit],
)
return m

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=p_port[bit],
o_O=port.p[bit],
)
return m

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_B=p_port[bit],
io_B=port.p[bit],
)
return m

@@ -575,48 +575,48 @@ def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
self._get_io_buffer(m, pin, port, attrs, i_invert=invert)
self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert)
return m

def get_output(self, pin, port, attrs, invert):
self._check_feature("single-ended output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
return m

def get_tristate(self, pin, port, attrs, invert):
self._check_feature("single-ended tristate", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
return m

def get_input_output(self, pin, port, attrs, invert):
self._check_feature("single-ended input/output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
self._get_io_buffer(m, pin, port, attrs, i_invert=invert, o_invert=invert)
self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert, o_invert=invert)
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
# See comment in should_skip_port_component above.
self._get_io_buffer(m, pin, p_port, attrs, i_invert=invert)
self._get_io_buffer(m, pin, port.p, attrs, i_invert=invert)
return m

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
# Note that the non-inverting output pin is not driven the same way as a regular
# output pin. The inverter introduces a delay, so for a non-inverting output pin,
# an identical delay is introduced by instantiating a LUT. This makes the waveform
# perfectly symmetric in the xdr=0 case.
self._get_io_buffer(m, pin, p_port, attrs, o_invert= invert, invert_lut=True)
self._get_io_buffer(m, pin, n_port, attrs, o_invert=not invert, invert_lut=True)
self._get_io_buffer(m, pin, port.p, attrs, o_invert= invert, invert_lut=True)
self._get_io_buffer(m, pin, port.n, attrs, o_invert=not invert, invert_lut=True)
return m

# Tristate bidirectional buffers are not supported on iCE40 because it requires external

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