Traceback (most recent call last):
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/cxxsim.py", line 137, in get_signal
    index = self.rtl_signals[signal]
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/hdl/ast.py", line 1560, in __getitem__
    return self._storage[key]
KeyError: <amaranth.hdl.ast.SignalKey (sig op)>

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/home/emil/school/pap/risc-je-zisk/main.py", line 70, in <module>
    with sim.write_vcd(f"{wavefilestem}.vcd", f"{wavefilestem}.gtkw", traces=[
  File "/usr/lib/python3.9/contextlib.py", line 119, in __enter__
    return next(self.gen)
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/cxxsim.py", line 277, in write_vcd
    self._state.get_signal(trace_signal)
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/cxxsim.py", line 139, in get_signal
    index = self._add_rtl_signal(signal)
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/cxxsim.py", line 109, in _add_rtl_signal
    assert all(part.type == signal_parts[0].type for part in signal_parts)
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/cxxsim.py", line 109, in <genexpr>
    assert all(part.type == signal_parts[0].type for part in signal_parts)
  File "/home/emil/.local/lib/python3.9/site-packages/amaranth/sim/_cxxrtl.py", line 86, in type
    return cxxrtl_type(self._type)
  File "/usr/lib/python3.9/enum.py", line 384, in __call__
    return cls.__new__(cls, value)
  File "/usr/lib/python3.9/enum.py", line 702, in __new__
    raise ve_exc
ValueError: 4 is not a valid cxxrtl_type