pysim2 doesn't write input signals to VCD

[nmigen-issue-migration]

Issue by adamgreig
Wednesday Dec 04, 2019 at 12:23 GMT
Originally opened as m-labs/nmigen#280

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Since updating to pysim2, any signals not driven from inside the fragment being simulated are not written to the VCD. This means signals which are inputs to the fragment and are driven by a sync process added to the simulator do not show up.

I think this is because FragmentCompiler is the only thing that adds signals to signal_names, but it is only called for the fragment the simulator is created with, not for any processes that are then added to the simulator. I might be misunderstanding the code though.

Additionally, as far as I can tell the traces argument to write_vcd is totally unused: it gets passed to _VCDWaveformWriter.__init__, which does nothing with it.

[nmigen-issue-migration]

Comment by whitequark
Wednesday Dec 04, 2019 at 12:31 GMT

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I think this is because FragmentCompiler is the only thing that adds signals to signal_names, but it is only called for the fragment the simulator is created with, not for any processes that are then added to the simulator. I might be misunderstanding the code though.

This is basically correct, but what it should do instead is also add any inputs. This wouldn't solve signals used for communicating between simulation processes only, but your suggestion wouldn't solve it as well because you can't add new signals in the middle of a vcd file.

Additionally, as far as I can tell the traces argument to write_vcd is totally unused: it gets passed to _VCDWaveformWriter.__init__, which does nothing with it.

Oops, good catch.

[nmigen-issue-migration]

Comment by phlipped
Tuesday Dec 10, 2019 at 11:17 GMT

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Would it be possible to just re-write the vcd file after simulation has finished such that the variable definitions section at the start contains any additional signals that were seen along the way?

[nmigen-issue-migration]

Comment by whitequark
Tuesday Dec 10, 2019 at 13:07 GMT

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Would it be possible to just re-write the vcd file after simulation has finished such that the variable definitions section at the start contains any additional signals that were seen along the way?

Maybe, but I'm not really interested in any solution that requires me to manually manipulate VCD files.

[nmigen-issue-migration]

Comment by JarrettBillingsley
Friday Dec 20, 2019 at 21:00 GMT

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Seems like the VCDWriter is a bit inflexible in this regard. I can imagine a version which buffers the variable changes and registered variables in memory until it's closed, at which point it then writes everything out. Not sure if that could be done with subclassing...

[edit] or, if not in memory, writing the variable changes to a temp file, and at close, outputs the registered variables and appends the contents of that temp file to the output. Dunno!

[nmigen-issue-migration]

Comment by adamgreig
Friday Dec 20, 2019 at 23:40 GMT

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I'm not really fussed about outputting signals that testbenches might create (at least, it doesn't affect me), but not having any input signals at all in the VCD makes my usual debugging/testing with pysim2 basically impossible at the moment.

[whitequark]

@adamgreig I fixed both issues you've reported. I'm sorry that such a critical issue ended up being open for so long.

[adamgreig]

Thank you!