Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Assigning local domain with different name #282

Closed
nmigen-issue-migration opened this issue Dec 17, 2019 · 0 comments
Closed

Assigning local domain with different name #282

nmigen-issue-migration opened this issue Dec 17, 2019 · 0 comments
Labels
Milestone

Comments

@nmigen-issue-migration
Copy link

Issue by Fatsie
Tuesday Dec 17, 2019 at 10:29 GMT
Originally opened as m-labs/nmigen#282


I have following code in nmigen:

#!/bin/env python3
from nmigen import *
from nmigen.back.verilog import convert

class CD1(Elaboratable):
    def __init__(self, localclk):
        self.d = Signal()
        self.q = Signal()

        self._clk = localclk

    def elaborate(self, platform):
        m = Module()

        m.domains.local = localcd = ClockDomain(local=True, reset_less=True)
        m.d.comb += localcd.clk.eq(self._clk)

        m.d.local += self.q.eq(self.d)

        return m

class CD2(Elaboratable):
    def __init__(self, localclk):
        self.d = Signal()
        self.q = Signal()

        self._clk = localclk

    def elaborate(self, platform):
        m = Module()

        localcd = ClockDomain(local=True, reset_less=True)
        m.domains.local = localcd
        m.d.comb += localcd.clk.eq(self._clk)

        m.d.local += self.q.eq(self.d)

        return m

class CD3(Elaboratable):
    def __init__(self, localclk):
        self.d = Signal()
        self.q = Signal()

        self._clk = localclk

    def elaborate(self, platform):
        m = Module()

        localcd = ClockDomain("local", local=True, reset_less=True)
        m.domains.local = localcd
        m.d.comb += localcd.clk.eq(self._clk)

        m.d.local += self.q.eq(self.d)

        return m


clk = Signal()
cd = CD1(clk)
with open("cd1.v", "w") as f:
    f.write(convert(cd, ports=(cd.d, cd.q, clk)))

clk = Signal()
cd = CD2(clk)
with open("cd2.v", "w") as f:
    f.write(convert(cd, ports=(cd.d, cd.q, clk)))

clk = Signal()
cd = CD3(clk)
with open("cd3.v", "w") as f:
    f.write(convert(cd, ports=(cd.d, cd.q, clk)))

For CD1 and CD3 I get the expected output but for CD2 I get the following output:

/* Generated by Yosys 0.9+932 (git sha1 ff8529a, gcc 4.8.5 -fPIC -Os) */

(* generator = "nMigen" *)
(* top =  1  *)
(* \nmigen.hierarchy  = "top" *)
module top(q, clk, local_clk, local_rst, d);
  (* src = "./cd.py:64" *)
  input clk;
  (* src = "./cd.py:24" *)
  input d;
  (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *)
  input local_clk;
  (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *)
  input local_rst;
  (* src = "./cd.py:32" *)
  wire localcd_clk;
  (* src = "./cd.py:25" *)
  output q;
  reg q = 1'h0;
  (* src = "./cd.py:25" *)
  reg \q$next ;
  always @(posedge local_clk)
      q <= \q$next ;
  always @* begin
    \q$next  = d;
    (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (local_rst)
      1'h1:
          \q$next  = 1'h0;
    endcase
  end
  assign localcd_clk = clk;
endmodule
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Development

No branches or pull requests

1 participant