Need a way to attach attributes to memories

[nmigen-issue-migration]

Issue by JarrettBillingsley
Wednesday Jan 01, 2020 at 19:38 GMT
Originally opened as m-labs/nmigen#291

---

For example, (* ram_block *) and (* logic_block *).

[whitequark]

@JarrettBillingsley Wish granted :)

Unfortunately, right now there is an issue with Yosys that prevents the attribute to be written out to Verilog. I'm working on that too.

[whitequark]

OK, so, to reiterate:

• to see memory attributes in nMigen Verilog output, you need write_verilog: dump $mem cell attributes YosysHQ/yosys#1683
• to have it used for iCE40 and ECP5, you need ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes YosysHQ/yosys#1603

[whitequark]

I'm going to reopen this until the upstream PRs are merged.

[whitequark]

Removing from milestone, as this only depends on upstream now.

[whitequark]

Triage: YosysHQ/yosys#1603 could be merged soon.

[whitequark]

Fixed upstream.

[JarrettBillingsley]

long-delayed followup: I used attrs = {"ram_block": True} on a Memory component and it worked! It forced it into a BRAM! Yay!