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Issue by ZirconiumX
Saturday Jan 11, 2020 at 17:13 GMT
Originally opened as m-labs/nmigen#302
from nmigen import *
from nmigen.back import verilog
self.i = Signal(8)
self.o = Signal(8)
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.eq(self.i << -3)
Traceback (most recent call last):
File "test.py", line 16, in <module>
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev13+g476ce15-py3.7.egg/nmigen/back/verilog.py", line 77, in convert
return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev13+g476ce15-py3.7.egg/nmigen/back/verilog.py", line 65, in _convert_rtlil_text
nmigen.back.verilog.YosysError: ERROR: Found error in internal cell \top.$3 ($sshl) at kernel/rtlil.cc:790:
attribute \src "test.py:12"
cell $sshl $3
parameter \Y_WIDTH 4'1011
parameter \B_WIDTH 2'11
parameter \B_SIGNED 1'1
parameter \A_WIDTH 4'1000
parameter \A_SIGNED 1'0
connect \Y $2
connect \B 3'101
connect \A \i
The text was updated successfully, but these errors were encountered:
The underlying cause is that RTLIL never supported signed shifts, but erroneously did not reject them in the validator. After YosysHQ/yosys#1551 got merged, our generated RTLIL became invalid.
There are two possible fixes here:
Sorry, something went wrong.
Honestly, I'd say that shifts by negative numbers definitely point to a bug. Really, you could get the equivalent of option 1 with a rotate operation, which I think would be clearer in semantics.
Everyone thinks we should ban them, so let's just do that.
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