fromenumimportEnumfromnmigenimport*fromnmigen.backimportverilogclassPiece(Enum):
BISHOP=2# Has to be specifically > 1 to crashclassSquare(Elaboratable):
def__init__(self):
self.i_piece=Signal(1)
defelaborate(self, platform):
m=Module()
withm.Switch(self.i_piece):
withm.Case(Piece.BISHOP): # Has to be this enum; inlining the value of 2 works finepassreturnmsq=Square()
print(verilog.convert(sq, ports=[sq.i_piece]))
This produces:
Traceback (most recent call last):
File "testcase.py", line 27, in <module>
print(verilog.convert(sq, ports=[sq.i_piece]))
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/back/verilog.py", line 76, in convert
rtlil_text = rtlil.convert(*args, **kwargs)
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/back/rtlil.py", line 1010, in convert
fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/hdl/ir.py", line 67, in get obj = obj.elaborate(platform)
File "testcase.py", line 20, in elaborate
pass
File "/usr/lib/python3.7/contextlib.py", line 119, in __exit__
next(self.gen)
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/hdl/dsl.py", line 264, in Switch
self._pop_ctrl()
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/hdl/dsl.py", line 405, in _pop_ctrl
src_loc=src_loc, case_src_locs=switch_case_src_locs))
File "/usr/local/lib/python3.7/dist-packages/nmigen-0.2.dev17+ge18385b-py3.7.egg/nmigen/hdl/ast.py", line 1296, in __init__
assert len(key) == len(self.test)
AssertionError
It minimised very oddly, but this is the smallest I could get it.
The text was updated successfully, but these errors were encountered:
Monday Jan 13, 2020 at 20:31 GMT
Originally opened as m-labs/nmigen#305
This produces:
It minimised very oddly, but this is the smallest I could get it.
The text was updated successfully, but these errors were encountered: