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Unclear error message on direction mismatch between Instance in submodule and toplevel usage #320

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rroohhh opened this issue Feb 15, 2020 · 1 comment
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@rroohhh
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rroohhh commented Feb 15, 2020

Executing the following snippet

from nmigen import *
from nmigen.back import verilog

class WrappedInstance(Elaboratable):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()

    def elaborate(self, _):
        m = Module()
        m.submodules += Instance("test", o_aout = self.a, o_bout = self.b)
        return m

m = Module()
m.submodules.instance = i = WrappedInstance()
m.d.comb += i.a.eq(i.b)

print(verilog.convert(m))

fails with this rather unclear error message:

Traceback (most recent call last):
  File "test.py", line 20, in <module>
    print(verilog.convert(m))
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/back/verilog.py", line 76, in convert
    rtlil_text = rtlil.convert(*args, **kwargs)
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/back/rtlil.py", line 1017, in convert
    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 533, in prepare
    fragment._propagate_ports(ports=(), all_undef_as_ports=True)
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 462, in _propagate_ports
    self._prepare_use_def_graph(parent, level, uses, defs, ios, self)
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 436, in _prepare_use_def_graph
    subfrag._prepare_use_def_graph(parent, level, uses, defs, ios, top)
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 428, in _prepare_use_def_graph
    add_defs(value._lhs_signals())
  File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 396, in add_defs
    assert defs[sig] is self
AssertionError

The problem is, that i.a and i.b were used by the instance as outputs, but in the toplevel module a is assigned to. The error message look similar to #191 but I am not sure this is actually the same bug.

@whitequark whitequark added the bug label Feb 15, 2020
@whitequark
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whitequark commented Feb 15, 2020

Different issue. I think @awygle also hit this one.

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