Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Integrate the CXXSim simulator #324

Open
8 of 15 tasks
whitequark opened this issue Feb 16, 2020 · 6 comments
Open
8 of 15 tasks

Integrate the CXXSim simulator #324

whitequark opened this issue Feb 16, 2020 · 6 comments
Labels
feature simulator:cxxsim

Comments

@whitequark
Copy link
Member

whitequark commented Feb 16, 2020 •
edited
Loading

A while ago I've implemented the Yosys cxxrtl backend, which is very similar to the current Python simulator conceptually while being significantly (10-100×) faster, competitive with Verilator.

nMigen should tightly integrate with this simulator, providing an interface identical to that of nmigen.sim.pysim.

CXXSim is currently developed in the cxxsim branch. You are encouraged to try it and report results!

Remaining tasks

See also #531 for Yosys-side view of these tasks.

Blockers (to be completed pre-merge)

  • CXXSim currently builds with -DNDEBUG because RTL contract violations (e.g. out of bounds memory reads) must not crash the host Python process. CXXRTL's VCD library currently ignores contract violations in NDEBUG builds, potentially hiding bugs.
  • CXXRTL design is reset (in response to a simulator reset) in an unreliable way because of missing CXXRTL-side API
  • VCD hierarchy does not match PySim's (missing top module)
  • .gtkw files are not written
  • write_vcd(traces=) are ignored
  • Reset values of undriven values are ignored
  • Simulator-only signals are not present in VCD files (cxxsim: simulator-only signals not included in VCD and GTKWave files #556)
  • Resetting CXXRTL design corrupts debug information (cxxsim: random garbage in memory traces #565)
  • CXXRTL-side Memory reads/writes from Python testbenches are not implemented in CXXSim (cxxsim: directly initializing memory #564)
  • Python testbenches trying to wait on CXXRTL values of certain types trigger assertion failures

Non-blockers (may be completed post-merge)
@whitequark whitequark added this to the 0.3 milestone Feb 16, 2020
@whitequark whitequark mentioned this issue Apr 27, 2020
Closed
whitequark added a commit that referenced this issue Aug 27, 2020
@whitequark
sim: split into base, core, and engines.
b65e11f 
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
@cestrauss

This comment has been minimized.

Sign in to view
@whitequark whitequark pinned this issue Nov 6, 2020
@whitequark whitequark changed the title Integrate cxxrtl simulator Integrate the CXXSim simulator Nov 6, 2020
@whitequark whitequark mentioned this issue Nov 6, 2020
Open
8 tasks
@whitequark
Copy link
Member Author

CXXSim no longer ignores contract violations, and uses an appropriate method to reset the simulation.

Prepending the top module in CXXSim VCD files will require upstream changes, see new task in #531.

@whitequark
Copy link
Member Author

VCD hierarchy in CXXSim and PySim now matches.

@whitequark
Copy link
Member Author

CXXSim now writes GTKW files.

@whitequark
Copy link
Member Author

CXXSim will not support race-free memory read/write operations; see #531 (comment) for details.

@whitequark whitequark mentioned this issue Dec 8, 2020
Closed
@whitequark whitequark mentioned this issue Dec 20, 2020
Open
@whitequark whitequark modified the milestones: 0.3, 0.4 Dec 14, 2021
@robtaylor
Copy link

I'm happy to have a look at it on mac when time is right..

@whitequark whitequark removed this from the 0.4 milestone Feb 3, 2023
@whitequark whitequark unpinned this issue Feb 13, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
feature simulator:cxxsim
Milestone
No milestone
Development

No branches or pull requests
3 participants
@whitequark @robtaylor @cestrauss