Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

pysim TypeError: unsupported operand type(s) for &: 'tuple' and 'int' #325

Closed
awygle opened this issue Feb 17, 2020 · 3 comments
Closed

Comments

@awygle
Copy link
Contributor

awygle commented Feb 17, 2020

After trying to replace some nmigen.compat.genlib.Record usages with nmigen.hdl.rec.Record, I'm getting this error when attempting to run the test_analyzer test case on my litescope port, as can be seen here: https://github.com/awygle/darkscope/tree/96eaaf9e72a2665e89e69237db42246c0a40bd79

Sorry for the terribleness of this bug report, but I couldn't manage to reduce the test case in any meaningful way....

@awygle
Copy link
Contributor Author

awygle commented Feb 18, 2020

Hooray, I reduced it to a test case that fits in an issue comment!

import unittest

from nmigen import *
from nmigen.hdl.rec import Record, DIR_FANOUT, DIR_FANIN, DIR_NONE, Layout
from nmigen.back.pysim import *

class Repro(unittest.TestCase):
    def test_repro(self):
        dut = Module()
        full_layout = [
            ("valid",   1, DIR_FANOUT),
            ("ready",   1, DIR_FANIN),
            ("payload", [("data", 1, DIR_FANOUT), ("hit", 1, DIR_FANOUT)]),
        ]
        src = Record(full_layout, name="testsrc")
        sink = Signal(src.shape().width)
        dut.d.sync += sink.eq(src)

        sim = Simulator(dut)
        sim.add_clock(1e-6, domain="sync")
        def process():
            yield Tick()
        sim.add_process(process)
        sim.run()

This is arguably not a sensible thing to do? But note that the opposite (src.eq(sink)) does not cause the error.

EDIT: you need the sub-record "payload" or this doesn't die, oops.

@awygle
Copy link
Contributor Author

awygle commented Feb 18, 2020

Okay, I messed it up again. The problem here is the empty subrecord:

import unittest

from nmigen import *
from nmigen.hdl.rec import Record, DIR_FANOUT, DIR_FANIN, DIR_NONE, Layout
from nmigen.back.pysim import *

class Repro(unittest.TestCase):
    def test_repro(self):
        dut = Module()
        full_layout = [
            ("valid",   1, DIR_FANOUT),
            ("ready",   1, DIR_FANIN),
            ("payload", [("data", 1, DIR_FANOUT), ("hit", 1, DIR_FANOUT)]),
            ("param", []),
        ]
        src = Record(full_layout, name="testsrc")
        sink = Signal(src.shape().width)
        dut.d.sync += sink.eq(src)

        sim = Simulator(dut)
        sim.add_clock(1e-6, domain="sync")
        def process():
            yield Tick()
        sim.add_process(process)
        sim.run()

If you remove the empty subrecord, the test passes.

@whitequark
Copy link
Member

whitequark commented Feb 19, 2020

Minimized:

from nmigen import *
from nmigen.back.pysim import *


dut = Module()
dut.d.comb += Signal().eq(Cat())
Simulator(dut).run()

@whitequark whitequark added this to the 0.3 milestone Apr 3, 2020
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Development

No branches or pull requests

2 participants