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This snippet illustrates the issue:
from nmigen import *
from nmigen.back import pysim
self.reg = Signal()
self.out = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.out.eq(~self.out)
# driving the signal fixes the issue
# uncomment: vcd will be correct
# m.d.comb += self.reg.eq(0)
bug = Bug()
fragment = Fragment.get(bug, None)
sim = pysim.Simulator(fragment)
with sim.write_vcd(vcd_file='bug.vcd', traces=[bug.out, bug.reg]):
sim.run_until(1e-6 * 10, run_passive=True)
With the line driving reg inside elaborate commented out, the generated VCD starts:
$comment Generated by nMigen $end
$date 2020-04-01 22:07:22.464464 $end
$timescale 100 ps $end
$var wire 1 3 r $end
$var wire 1 4 e $end
$var wire 1 5 g $end
$scope module top $end
$var wire 1 0 clk $end
$var wire 1 1 rst $end
$var wire 1 2 out $end
i.e. reg has somehow become three signals, r, e and g.
Driving reg combinatorically or with registered logic fixes the signal's name and value in the VCD.
The text was updated successfully, but these errors were encountered:
Experimenting, it appears this happens if the signal is unused in any way - either undriven, or not part of the module's logic.
Sorry, something went wrong.
Ouch, I think I made a mistake fixing #280.
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