You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This is an unavoidable limitation caused by the fact that module ports have per-port direction (in RTLIL, Verilog, etc), but your code would only work if they had per-bit direction. See also #191.
Hopefully this isn't just me doing something wrong, but, the following snippet
produces the error
bug.py:16: DriverConflict: Signal '(sig xo)' is driven from multiple fragments: top.<unnamed #0>, top.<unnamed #1>; hierarchy will be flattened
despite each individual bit of
xo
only being driven in one location.The text was updated successfully, but these errors were encountered: