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DriverConflict raised on entire signal when independently driving individual bits from submodules #347

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the6p4c opened this issue Apr 5, 2020 · 2 comments
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@the6p4c
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the6p4c commented Apr 5, 2020

Hopefully this isn't just me doing something wrong, but, the following snippet

from nmigen import *

class MySubmodule(Elaboratable):
    def __init__(self, o):
        self.o = o

    def elaborate(self, platform):
        m = Module()
        m.d.comb += self.o.eq(1)
        return m

class Bug(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        xo = Signal(2)
        m.submodules += [
            MySubmodule(xo[0]),
            MySubmodule(xo[1])
        ]

        return m

from nmigen.back import verilog
verilog.convert(Fragment.get(Bug(), None))

produces the error

bug.py:16: DriverConflict: Signal '(sig xo)' is driven from multiple fragments: top.<unnamed #0>, top.<unnamed #1>; hierarchy will be flattened

despite each individual bit of xo only being driven in one location.

@whitequark
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whitequark commented Apr 6, 2020

This is an unavoidable limitation caused by the fact that module ports have per-port direction (in RTLIL, Verilog, etc), but your code would only work if they had per-bit direction. See also #191.

@whitequark
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whitequark commented Apr 6, 2020

Someone on IRC (mwk?) suggested that this could be worked around using inout ports, but this would cause all sorts of issues downstream.

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