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bit_select and word_select behave differently #351

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x44203 opened this issue Apr 11, 2020 · 1 comment
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bit_select and word_select behave differently #351

x44203 opened this issue Apr 11, 2020 · 1 comment
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@x44203
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x44203 commented Apr 11, 2020

The commented-out word_select shoud behave the same as the bit_select but the bit_select throws a "IndexError: Cannot stop slice 9 bits into 8-bit value" while the word_select compiles just fine.

class Test(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        datain = Signal(4)
        dataout = Signal(8)
        assert len(dataout) % len(datain) == 0
        counter = Signal()
        #m.d.sync += dataout.word_select(counter, 4).eq(datain)
        m.d.sync += dataout.bit_select(counter * 4, 4).eq(datain)
        return m

FPGA.ECP55GEVNPlatform().build(Test())
@whitequark whitequark added the bug label Apr 11, 2020
@whitequark
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whitequark commented Apr 11, 2020

Interestingly the codegen for word_select appears to be broken too.

@whitequark whitequark added this to the 0.3 milestone Apr 13, 2020
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