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Python chokes on simulated memories of depth greater than ~3k #359
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Yep, this is a known pysim issue that requires reworking the way memories are translated. |
This adds a simple RISC-V system with RAM, ROM, and a seven-segment display driver peripheral. The GCC toolchain is integrated into the build and is used to pre-program the ROM with a simple program that writes "deadbeef" to the display. Also included is a bridge to drive JTAG over the on-board UART. This requires opening a socket atop the TTY (e.g. with socat) and connecting to this using OpenOCD's bitbang driver. GDB can connect and see some system state -- it can dump registers and CSRs, read and write memory over the data bus -- but many things don't work yet, including stepping. RAM and ROM are provided by Xilinx block RAM primitives, which are 32 kib or 4 kiB. However, due to amaranth-lang/amaranth#359, this is reduced to 2 kiB to make Python simulation work.
Interesting, I thought this would work on 3.7 (https://bugs.python.org/issue31113) but it doesn't. |
Observed the same problem. Can workaround for now by calling |
Just to add a few notes to this to help with people finding it from google: On a Core i9 MBP (2019) this makes simulations of memory with a depth of 2**13 (just a lookup table) take about 1 minute if the recursion limit is set high enough. Python version is You can expect to see an exception which looks something like this:
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Current the value compiler translates ArrayProxy into if-elif trees which can cause the compiler to crash due to deep recursion (#359). After this commit, it instead translates them into pattern matching when it is supported (on Python >= 3.10) to avoid this problem.
With Python 3.7.3 (shipped with Debian stable) and 3.8.2 (via pyenv), I encountered the following error when simulating a design with a couple of memory banks:
Here's a minimal reproduction:
Reducing the depth of the memory (width doesn't seem to matter) makes the failure go away. For the time being that workaround works for me, but it would be nice to use the same design parameters for simulation and synthesis.
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